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From: Cyril Chemparathy <cyril@ti.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <nico@linaro.org>,
	<will.deacon@arm.com>, <catalin.marinas@arm.com>,
	Vitaly Andrianov <vitalya@ti.com>
Subject: Re: [RFC 23/23] ARM: keystone: add switch over to high physical address range
Date: Tue, 24 Jul 2012 10:59:17 -0400	[thread overview]
Message-ID: <500EB845.3020600@ti.com> (raw)
In-Reply-To: <201207241439.25314.arnd@arndb.de>

On 7/24/2012 10:39 AM, Arnd Bergmann wrote:
> On Tuesday 24 July 2012, Cyril Chemparathy wrote:
>> Keystone platforms have their physical memory mapped at an address outside the
>> 32-bit physical range.  A Keystone machine with 16G of RAM would find its
>> memory at 0x0800000000 - 0x0bffffffff.
>>
>> For boot purposes, the interconnect supports a limited alias of some of this
>> memory within the 32-bit addressable space (0x80000000 - 0xffffffff).  This
>> aliasing is implemented in hardware, and is not intended to be used much
>> beyond boot.  For instance, DMA coherence does not work when running out of
>> this aliased address space.
>>
>> Therefore, we've taken the approach of booting out of the low physical address
>> range, and subsequently we switch over to the high range once we're safely
>> inside machine specific territory.  This patch implements this switch over
>> mechanism, which involves rewiring the TTBRs and page tables to point to the
>> new physical address space.
>>
>> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
>> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
>
> I think this needs some more explanations. Why is not not possible
> to use this the larger area from the start when we first enable
> paging?

By enable paging, I assume you refer to the head.S init.  For this the 
boot code needs to get the "real physical address" from somewhere 
instead of having to deduce it from the program counter.  We could do 
this by parsing DTB in the decompressor, and passing in a 64-bit physmem 
pointer into the kernel startup code.

We'd considered this approach (at least briefly), but then balked at (a) 
having to change the entry conditions into head.S code, and (b) baking 
in dependencies on the decompressor.

> Also, the code does not really look platform specific, so I could
> imagine that if you need it, other similar platforms will need the
> same thing, and it should be put into common code and enabled
> all the time when using LPAE.
>

Absolutely agreed.  Vitaly and I have been trying to work it out this 
way, and we hope to have something more common in the next version of 
this series.

> 	Arnd
>

-- 
Thanks
- Cyril

  reply	other threads:[~2012-07-24 14:59 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-24  1:09 [RFC 00/23] Introducing the TI Keystone platform Cyril Chemparathy
2012-07-24  1:09 ` [RFC 01/23] ARM: LPAE: disable phys-to-virt patching on PAE systems Cyril Chemparathy
2012-07-24  9:41   ` Catalin Marinas
2012-07-24 10:43     ` Cyril Chemparathy
2012-07-24  1:09 ` [RFC 02/23] ARM: LPAE: use signed arithmetic for mask definitions Cyril Chemparathy
2012-07-24 10:05   ` Catalin Marinas
2012-07-24 10:52     ` Cyril Chemparathy
2012-07-31 15:35     ` Cyril Chemparathy
2012-07-24  1:09 ` [RFC 03/23] ARM: LPAE: use phys_addr_t on virt <--> phys conversion Cyril Chemparathy
2012-07-24 10:37   ` Catalin Marinas
2012-07-24 10:55     ` Cyril Chemparathy
2012-07-24 11:02       ` Catalin Marinas
2012-07-24  1:09 ` [RFC 04/23] ARM: LPAE: use phys_addr_t in alloc_init_pud() Cyril Chemparathy
2012-07-24  1:09 ` [RFC 05/23] ARM: LPAE: use phys_addr_t in free_memmap() Cyril Chemparathy
2012-07-24  1:09 ` [RFC 06/23] ARM: LPAE: use phys_addr_t for initrd location and size Cyril Chemparathy
2012-07-24  1:09 ` [RFC 07/23] ARM: LPAE: use phys_addr_t for membank size Cyril Chemparathy
2012-07-24 10:04   ` Will Deacon
2012-07-24 10:46     ` Cyril Chemparathy
2012-07-24  1:09 ` [RFC 08/23] ARM: LPAE: use 64-bit pgd physical address in switch_mm() Cyril Chemparathy
2012-07-24  1:09 ` [RFC 09/23] ARM: LPAE: use 64-bit accessors for TTBR registers Cyril Chemparathy
2012-07-24  1:09 ` [RFC 10/23] ARM: mm: use physical addresses in highmem sanity checks Cyril Chemparathy
2012-07-24  1:09 ` [RFC 11/23] ARM: mm: cleanup checks for membank overlap with vmalloc area Cyril Chemparathy
2012-07-24  1:09 ` [RFC 12/23] ARM: mm: clean up membank size limit checks Cyril Chemparathy
2012-07-24  1:09 ` [RFC 13/23] ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem Cyril Chemparathy
2012-07-24  1:09 ` [RFC 14/23] ARM: LPAE: factor out T1SZ and TTBR1 computations Cyril Chemparathy
2012-07-24  1:09 ` [RFC 15/23] ARM: LPAE: allow proc override of TTB setup Cyril Chemparathy
2012-07-24  1:09 ` [RFC 16/23] ARM: LPAE: accomodate >32-bit addresses for page table base Cyril Chemparathy
2012-07-24  1:09 ` [RFC 17/23] ARM: add machine desc hook for early memory/paging initialization Cyril Chemparathy
2012-07-24 14:32   ` Arnd Bergmann
2012-07-24 14:47     ` Cyril Chemparathy
2012-07-24  1:09 ` [RFC 18/23] ARM: add virt_to_idmap for interconnect aliasing Cyril Chemparathy
2012-07-24  1:09 ` [RFC 19/23] drivers: cma: fix addressing on PAE machines Cyril Chemparathy
2012-07-24  1:09 ` [RFC 20/23] mm: bootmem: use phys_addr_t for physical addresses Cyril Chemparathy
2012-07-24  1:09 ` [RFC 21/23] ARM: keystone: introducing TI Keystone platform Cyril Chemparathy
2012-07-24 14:46   ` Arnd Bergmann
2012-07-24 17:56     ` Cyril Chemparathy
2012-07-24 18:45       ` Arnd Bergmann
2012-07-24  1:09 ` [RFC 22/23] ARM: keystone: enable SMP on Keystone machines Cyril Chemparathy
2012-07-24  1:09 ` [RFC 23/23] ARM: keystone: add switch over to high physical address range Cyril Chemparathy
2012-07-24  9:49   ` Catalin Marinas
2012-07-24 14:39   ` Arnd Bergmann
2012-07-24 14:59     ` Cyril Chemparathy [this message]
2012-07-24  9:08 ` [RFC 00/23] Introducing the TI Keystone platform Will Deacon
2012-07-24 10:41   ` Cyril Chemparathy

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