From: Lu Baolu <baolu.lu@linux.intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
"Pan, Jacob jun" <jacob.jun.pan@intel.com>,
"Raj, Ashok" <ashok.raj@intel.com>,
"Liu, Yi L" <yi.l.liu@intel.com>
Cc: baolu.lu@linux.intel.com,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/4] iommu/vt-d: Check before setting PGSNP bit in pasid table entry
Date: Fri, 22 Apr 2022 21:04:11 +0800 [thread overview]
Message-ID: <503795b0-282c-2a8a-b669-5e7a0fc4a696@linux.intel.com> (raw)
In-Reply-To: <BN9PR11MB52767A16DC6BB80838C876068CF79@BN9PR11MB5276.namprd11.prod.outlook.com>
On 2022/4/22 10:47, Tian, Kevin wrote:
>> From: Lu Baolu
>> Sent: Thursday, April 21, 2022 7:36 PM
>>
>> The latest VT-d specification states that the PGSNP field in the pasid
>> table entry should be treated as Reserved(0) for implementations not
>> supporting Snoop Control (SC=0 in the Extended Capability Register).
>> This adds a check before setting the field.
>>
>> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>
>> ---
>> drivers/iommu/intel/pasid.c | 13 ++++++++++---
>> 1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
>> index f8d215d85695..5cb2daa2b8cb 100644
>> --- a/drivers/iommu/intel/pasid.c
>> +++ b/drivers/iommu/intel/pasid.c
>> @@ -625,8 +625,14 @@ int intel_pasid_setup_first_level(struct intel_iommu
>> *iommu,
>> }
>> }
>>
>> - if (flags & PASID_FLAG_PAGE_SNOOP)
>> - pasid_set_pgsnp(pte);
>> + if (flags & PASID_FLAG_PAGE_SNOOP) {
>> + if (ecap_sc_support(iommu->ecap)) {
>> + pasid_set_pgsnp(pte);
>> + } else {
>> + pasid_clear_entry(pte);
>> + return -EINVAL;
>> + }
>> + }
>>
>> pasid_set_domain_id(pte, did);
>> pasid_set_address_width(pte, iommu->agaw);
>> @@ -710,7 +716,8 @@ int intel_pasid_setup_second_level(struct
>> intel_iommu *iommu,
>> pasid_set_fault_enable(pte);
>> pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
>>
>> - if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
>> + if (ecap_sc_support(iommu->ecap) &&
>> + domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
>> pasid_set_pgsnp(pte);
>>
> This should be rebased on top of Jason's enforce coherency series
> instead of blindly setting it. No matter whether it's legacy mode
> where we set SNP in PTE or scalable mode where we set PGSNP
> in PASID entry for entire page table, the trigger point should be
> same i.e. when someone calls enforce_cache_coherency().
With Jason's enforce coherency series merged, we even don't need to set
PGSNP bit of a pasid entry for second level translation. 2nd level
always supports SNP in PTEs, so set PGSNP in pasid table entry is
unnecessary.
Any thoughts?
Best regards,
baolu
next prev parent reply other threads:[~2022-04-22 13:04 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-21 11:35 [PATCH v2 0/4] iommu/vt-d: Some fine tuning of SVA Lu Baolu
2022-04-21 11:35 ` [PATCH v2 1/4] iommu/vt-d: Check before setting PGSNP bit in pasid table entry Lu Baolu
2022-04-22 2:47 ` Tian, Kevin
2022-04-22 13:04 ` Lu Baolu [this message]
2022-04-24 3:37 ` Tian, Kevin
2022-04-24 4:37 ` Lu Baolu
2022-04-24 5:55 ` Tian, Kevin
2022-04-24 6:23 ` Lu Baolu
2022-04-21 11:35 ` [PATCH v2 2/4] iommu/vt-d: Set PGSNP bit in pasid table entry for SVA binding Lu Baolu
2022-04-22 3:05 ` Tian, Kevin
2022-04-22 13:13 ` Lu Baolu
2022-04-21 11:35 ` [PATCH v2 3/4] iommu/vt-d: Drop stop marker messages Lu Baolu
2022-04-22 3:05 ` Tian, Kevin
2022-04-23 7:32 ` Lu Baolu
2022-04-21 11:35 ` [PATCH v2 4/4] iommu/vt-d: Size Page Request Queue to avoid overflow condition Lu Baolu
2022-04-22 3:07 ` Tian, Kevin
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