Re: [PATCH v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc

[Alexander Stein <alexander.stein@ew.tq-group.com>]

Hi everyone,

Am Mittwoch, 28. Januar 2026, 15:47:08 CET schrieb Mark Brown:
> On Wed, Jan 28, 2026 at 03:09:46PM +0100, Nicolas Frattaroli wrote:
> > On Wednesday, 28 January 2026 00:14:29 Central European Standard Time Mark Brown wrote:
> 
> > > Do you have a debugging patch we could run which would say which clocks
> > > are impacted?  I guess it's more of an issue for the platforms that give
> > > no output but for at least Avenger96 I was getting earlycon output.
> 
> > Try this one
> 
> For the Avenger96 that says:
> 
> [    0.347816] __clk_core_init: enabling parent ck_hse for ck_per
> [    0.352230] __clk_core_init: disabling parent ck_hse for ck_per
> [    0.358207] __clk_core_init: enabling parent pll1_p for ck_mpu
> [    0.364005] __clk_core_init: disabling parent pll1_p for ck_mpu
> 
> https://lava.sirena.org.uk/scheduler/job/2412562#L563
> 

This is for TQMa8MPxL/MBa8MPxL:

[    1.452788] __clk_core_init: enabling parent audio_pll1_out for clkout1_sel
[    1.457677] __clk_core_init: disabling parent audio_pll1_out for clkout1_sel
[    1.464270] __clk_core_init: enabling parent audio_pll1_out for clkout2_sel
[    1.471760] __clk_core_init: disabling parent audio_pll1_out for clkout2_sel
[    1.478360] __clk_core_init: enabling parent sys_pll2_500m for arm_a53_div
[    1.485259] __clk_core_init: disabling parent sys_pll2_500m for arm_a53_div

Best regards,
Alexander

-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/