* [PATCH] ioat: remove chanerr mask setting for IOAT v3.x
@ 2012-11-16 23:26 Dave Jiang
2012-11-27 4:56 ` Dan Williams
0 siblings, 1 reply; 4+ messages in thread
From: Dave Jiang @ 2012-11-16 23:26 UTC (permalink / raw)
To: djbw; +Cc: vinod.koul, linux-kernel
The CHANERRMSK_INT register should be 0. The existing code set a value
for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that
has been fixed when the hardware was released. There is no need for this
code.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/dma/ioat/dma_v3.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index f7f1dc6..60c15c4 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -1126,12 +1126,8 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan)
chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
- /* -= IOAT ver.3 workarounds =- */
- /* Write CHANERRMSK_INT with 3E07h to mask out the errors
- * that can cause stability issues for IOAT ver.3, and clear any
- * pending errors
- */
- pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
+ /* clearn CHANERRMASK_INT and clear any pending errors */
+ pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0);
err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
if (err) {
dev_err(&pdev->dev, "channel error register unreachable\n");
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] ioat: remove chanerr mask setting for IOAT v3.x
2012-11-16 23:26 [PATCH] ioat: remove chanerr mask setting for IOAT v3.x Dave Jiang
@ 2012-11-27 4:56 ` Dan Williams
2012-11-27 6:21 ` Jiang, Dave
2012-11-27 21:24 ` Dave Jiang
0 siblings, 2 replies; 4+ messages in thread
From: Dan Williams @ 2012-11-27 4:56 UTC (permalink / raw)
To: Dave Jiang; +Cc: vinod.koul, linux-kernel
On Fri, Nov 16, 2012 at 3:26 PM, Dave Jiang <dave.jiang@intel.com> wrote:
> The CHANERRMSK_INT register should be 0. The existing code set a value
> for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that
> has been fixed when the hardware was released. There is no need for this
> code.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
>
> drivers/dma/ioat/dma_v3.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
> index f7f1dc6..60c15c4 100644
> --- a/drivers/dma/ioat/dma_v3.c
> +++ b/drivers/dma/ioat/dma_v3.c
> @@ -1126,12 +1126,8 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan)
> chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
> writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
>
> - /* -= IOAT ver.3 workarounds =- */
> - /* Write CHANERRMSK_INT with 3E07h to mask out the errors
> - * that can cause stability issues for IOAT ver.3, and clear any
> - * pending errors
> - */
> - pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
> + /* clearn CHANERRMASK_INT and clear any pending errors */
> + pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0);
Can we get rid of this write / register access altogether? Then the
driver will load on systems where extended pci configuration space is
not available.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] ioat: remove chanerr mask setting for IOAT v3.x
2012-11-27 4:56 ` Dan Williams
@ 2012-11-27 6:21 ` Jiang, Dave
2012-11-27 21:24 ` Dave Jiang
1 sibling, 0 replies; 4+ messages in thread
From: Jiang, Dave @ 2012-11-27 6:21 UTC (permalink / raw)
To: Dan Williams; +Cc: Koul, Vinod, linux-kernel@vger.kernel.org
On Nov 26, 2012, at 9:56 PM, "Dan Williams" <djbw@fb.com> wrote:
> On Fri, Nov 16, 2012 at 3:26 PM, Dave Jiang <dave.jiang@intel.com> wrote:
>> The CHANERRMSK_INT register should be 0. The existing code set a value
>> for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that
>> has been fixed when the hardware was released. There is no need for this
>> code.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>>
>> drivers/dma/ioat/dma_v3.c | 8 ++------
>> 1 file changed, 2 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
>> index f7f1dc6..60c15c4 100644
>> --- a/drivers/dma/ioat/dma_v3.c
>> +++ b/drivers/dma/ioat/dma_v3.c
>> @@ -1126,12 +1126,8 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan)
>> chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
>> writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
>>
>> - /* -= IOAT ver.3 workarounds =- */
>> - /* Write CHANERRMSK_INT with 3E07h to mask out the errors
>> - * that can cause stability issues for IOAT ver.3, and clear any
>> - * pending errors
>> - */
>> - pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
>> + /* clearn CHANERRMASK_INT and clear any pending errors */
>> + pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0);
>
> Can we get rid of this write / register access altogether? Then the
> driver will load on systems where extended pci configuration space is
> not available.
Yes I will generate new patch.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] ioat: remove chanerr mask setting for IOAT v3.x
2012-11-27 4:56 ` Dan Williams
2012-11-27 6:21 ` Jiang, Dave
@ 2012-11-27 21:24 ` Dave Jiang
1 sibling, 0 replies; 4+ messages in thread
From: Dave Jiang @ 2012-11-27 21:24 UTC (permalink / raw)
To: Dan Williams; +Cc: vinod.koul, linux-kernel
On 11/26/2012 09:56 PM, Dan Williams wrote:
> On Fri, Nov 16, 2012 at 3:26 PM, Dave Jiang <dave.jiang@intel.com> wrote:
>> The CHANERRMSK_INT register should be 0. The existing code set a value
>> for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that
>> has been fixed when the hardware was released. There is no need for this
>> code.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>>
>> drivers/dma/ioat/dma_v3.c | 8 ++------
>> 1 file changed, 2 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
>> index f7f1dc6..60c15c4 100644
>> --- a/drivers/dma/ioat/dma_v3.c
>> +++ b/drivers/dma/ioat/dma_v3.c
>> @@ -1126,12 +1126,8 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan)
>> chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
>> writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
>>
>> - /* -= IOAT ver.3 workarounds =- */
>> - /* Write CHANERRMSK_INT with 3E07h to mask out the errors
>> - * that can cause stability issues for IOAT ver.3, and clear any
>> - * pending errors
>> - */
>> - pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
>> + /* clearn CHANERRMASK_INT and clear any pending errors */
>> + pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0);
> Can we get rid of this write / register access altogether? Then the
> driver will load on systems where extended pci configuration space is
> not available.
So this entire thing does read and write to a mask register and the
error register. Were you wanting both removed? I think we may still want
to clear the error register. If that's the case, it doesn't get around
the extended PCI config space issue.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2012-11-27 21:24 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2012-11-16 23:26 [PATCH] ioat: remove chanerr mask setting for IOAT v3.x Dave Jiang
2012-11-27 4:56 ` Dan Williams
2012-11-27 6:21 ` Jiang, Dave
2012-11-27 21:24 ` Dave Jiang
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