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Date: Thu, 24 Jan 2013 10:20:47 +0800
From: Yijing Wang <wangyijing@huawei.com>
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To: Randy Dunlap <rdunlap@infradead.org>
CC: Rob Landley <rob@landley.net>, Bjorn Helgaas <bhelgaas@google.com>,
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        Jon Mason <jdmason@kudzu.us>, <linux-pci@vger.kernel.org>,
        Andrew Murray <andrew.murray@arm.com>,
        Hanjun Guo <guohanjun@huawei.com>, <jiang.liu@huawei.com>
Subject: Re: [Update][PATCH] PCI: Document PCIE BUS MPS parameters
References: <1358944092-28884-1-git-send-email-wangyijing@huawei.com> <510074C7.6090203@infradead.org> <510094A4.3040806@huawei.com> <51009645.5040406@infradead.org>
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On 2013/1/24 10:02, Randy Dunlap wrote:
> On 01/23/13 17:55, Yijing Wang wrote:
>> Hi Randy,
>>    Thanks for your review and comments! please refer to inlined comments below.
>>
>> On 2013/1/24 7:39, Randy Dunlap wrote:
>>> On 01/23/13 04:28, Yijing Wang wrote:
> 
>>>
>>> What is (are) MRRS?
>>
>> MRRS is "Max Read Request Size" and MPS is "Max Payload Size".
>> Need use "Max Read Request Size" instead of MRRS ?
> 
> Where is MRRS documented?

The description of MRRS can be found at PCIe Spec 2.0/3.0 7.8.4 Device Control Register.

> 
> I would probably do it like so:
> 
> Also set MRRS (Max Read Request Size) to the ....

Hmm, I will explain MPS and MRRS when they appear first time like,

pcie_bus_tune_off   Disable PCIe MPS (Max Payload Size) turning and using
		the BIOS-configured MPS defaults.

pcie_bus_perf	......Also set MRRS (Max Read Request Size) to the......

Thanks!
Yijing

> 


-- 
Thanks!
Yijing