From: Krzysztof Kozlowski <krzk@kernel.org>
To: Willie Thai <wthai@nvidia.com>,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
joel@jms.id.au, andrew@codeconstruct.com.au, kees@kernel.org,
tony.luck@intel.com, gpiccoli@igalia.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
linux-hardening@vger.kernel.org, openbmc@lists.ozlabs.org
Cc: leohu@nvidia.com, tingkaic@nvidia.com, dkodihalli@nvidia.com,
Mars Yang <maryang@nvidia.com>, Andrew Lunn <andrew@lunn.ch>,
Paul Menzel <pmenzel@molgen.mpg.de>
Subject: Re: [PATCH v3 1/2] ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC
Date: Fri, 21 Mar 2025 08:44:21 +0100 [thread overview]
Message-ID: <5127f2e7-cb38-4103-8799-551fdedd8152@kernel.org> (raw)
In-Reply-To: <20250320164633.101331-2-wthai@nvidia.com>
On 20/03/2025 17:46, Willie Thai wrote:
> +
> + leds {
> + compatible = "gpio-leds";
> + led-0 {
> + label = "uid_led";
> + gpios = <&sgpiom0 27 GPIO_ACTIVE_LOW>;
> + };
> + led-1 {
> + label = "fault_led";
> + gpios = <&sgpiom0 29 GPIO_ACTIVE_LOW>;
> + };
> + led-2 {
> + label = "power_led";
> + gpios = <&sgpiom0 31 GPIO_ACTIVE_LOW>;
> + };
> +
You still have stray blank lines in few places.
> + };
> +
> + buttons {
> + button-power {
> + label = "power-btn";
> + gpio = <&sgpiom0 156 GPIO_ACTIVE_LOW>;
> + };
> + button-uid {
> + label = "uid-btn";
> + gpio = <&sgpiom0 154 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> +};
> +
...
> +/*
> + * Enable USB port A as device (via the virtual hub) to host
> + */
> +&vhub {
> + status = "okay";
> + pinctrl-names = "default";
> + /*
> + * Uncomment below line to enable internal EHCI controller
> + * Current config uses xHCI Port1
> + */
Comment makes no sense.
> +};
> +
> +&video {
> + status = "okay";
> + memory-region = <&video_engine_memory>;
> +};
> +
...
> +&gpio0 {
> + gpio-line-names =
> + /*A0-A7*/ "", "", "", "", "", "", "", "",
> + /*B0-B7*/ "", "", "", "", "", "", "", "",
> + /*C0-C7*/ "SGPIO_I2C_MUX_SEL-O", "", "", "", "", "", "", "",
> + /*D0-D7*/ "", "", "", "UART1_MUX_SEL-O", "", "FPGA_PEX_RST_L-O", "", "",
> + /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "UART3_MUX_SEL-O",
> + "", "", "", "SGPIO_BMC_EN-O",
> + /*F0-F7*/ "", "", "", "", "", "", "", "",
> + /*G0-G7*/ "", "", "", "", "", "", "", "",
> + /*H0-H7*/ "", "", "", "", "", "", "", "",
> + /*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "GLOBAL_WP_BMC-O", "BMC_DDR4_TEN-O",
> + /*J0-J7*/ "", "", "", "", "", "", "", "",
> + /*K0-K7*/ "", "", "", "", "", "", "", "",
> + /*L0-L7*/ "", "", "", "", "", "", "", "",
> + /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "HMC_RESET_L-O", "STBY_POWER_EN-O",
> + "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "",
> + /*N0-N7*/ "", "", "", "", "", "", "", "",
> + /*O0-O7*/ "", "", "", "", "", "", "", "",
> + /*P0-P7*/ "", "", "", "", "", "", "", "",
> + /*Q0-Q7*/ "", "", "", "", "", "", "", "",
> + /*R0-R7*/ "", "", "", "", "", "", "", "",
> + /*S0-S7*/ "", "", "", "", "", "", "", "",
> + /*T0-T7*/ "", "", "", "", "", "", "", "",
> + /*U0-U7*/ "", "", "", "", "", "", "", "",
> + /*V0-V7*/ "AP_EROT_REQ-O", "EROT_AP_GNT-I", "", "","PCB_TEMP_ALERT-I", "","", "",
> + /*W0-W7*/ "", "", "", "", "", "", "", "",
> + /*X0-X7*/ "", "", "TPM_MUX_SEL-O", "", "", "", "", "",
> + /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "","", "", "",
> + /*Z0-Z7*/ "BMC_READY-O","", "", "", "", "", "", "";
> +};
> +
> +&gpio1 {
> + /* 36 1.8V GPIOs */
> + gpio-line-names =
> + /*A0-A7*/ "", "", "", "", "", "", "", "",
> + /*B0-B7*/ "", "", "", "", "", "", "IO_EXPANDER_INT_L-I","",
> + /*C0-C7*/ "", "", "", "", "", "", "", "",
> + /*D0-D7*/ "", "", "", "", "", "", "SPI_HOST_TPM_RST_L-O", "SPI_BMC_FPGA_INT_L-I",
> + /*E0-E7*/ "", "", "", "", "", "", "", "";
> +};
> +
> +// EMMC group that excludes WP pin
> +&pinctrl {
> + pinctrl_emmcg5_default: emmcg5_default {
No underscores in node names.
> + function = "EMMC";
> + groups = "EMMCG5";
> + };
> +};
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-03-21 7:44 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-20 16:46 [PATCH v3 0/2] Add device tree for Nvidia's GB200NVL BMC Willie Thai
2025-03-20 16:46 ` [PATCH v3 1/2] ARM: dts: aspeed: " Willie Thai
2025-03-20 16:54 ` Andrew Lunn
2025-03-21 7:44 ` Krzysztof Kozlowski [this message]
2025-03-20 16:46 ` [PATCH v3 2/2] dt-bindings: arm: aspeed: add " Willie Thai
2025-03-21 1:06 ` Andrew Jeffery
2025-03-21 5:27 ` Willie Thai
2025-03-21 9:40 ` Krzysztof Kozlowski
2025-03-20 18:26 ` [PATCH v3 0/2] Add device tree for " Rob Herring (Arm)
2025-03-21 1:06 ` Andrew Jeffery
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