Re: [PATCH 2/2] PCI: fix system hang issue of Marvell SATA host controller

Myron Stowe
2013-03-14T15:03:56Z

On Wed, Mar 13, 2013 at 3:40 AM, Xiangliang Yu <yuxiangl@marvell.com> wrote:
> Hi, Bjorn
>
>> >> > Now, the situation is like this:
>> >> > I captured the PCIE trace with analyzer and found that 1st BE is 0x1111
>> >> > when
>> >> > accessing IO port space. But 9125 spec has some limitation, and the BE
>> >> > must
>> >> > be
>> >> > 0x0100, to access the 2nd byte only. So, the chip will go to bad.
>> >>
>> >> Great, this is new, interesting, data. Is the 9125 spec publicly
>> >> accessible and/or could you elaborate on the "some limitation"
>> >> comment?
>> > 9125 spec is publicly accessible.
> If you can't see the pic, please open the attachment. Thanks!

Neither Bjorn nor myself could see the pic (from the previous thread
or this thread's attachment).

>
>