Re: [PATCH 2/2] PCI: fix system hang issue of Marvell SATA host controller

Myron Stowe
2013-03-21T16:00:52Z

On Sat, Mar 16, 2013 at 6:13 PM, Myron Stowe <myron.stowe@gmail.com> wrote:
> On Thu, Mar 14, 2013 at 9:03 AM, Myron Stowe <myron.stowe@gmail.com> wrote:
>> On Wed, Mar 13, 2013 at 3:40 AM, Xiangliang Yu <yuxiangl@marvell.com> wrote:
>>> Hi, Bjorn
>>>
>>>> >> > Now, the situation is like this:
>>>> >> > I captured the PCIE trace with analyzer and found that 1st BE is 0x1111
>>>> >> > when
>>>> >> > accessing IO port space. But 9125 spec has some limitation, and the BE
>>>> >> > must
>>>> >> > be
>>>> >> > 0x0100, to access the 2nd byte only. So, the chip will go to bad.
>>>> >>
>>>> >> Great, this is new, interesting, data. Is the 9125 spec publicly
>>>> >> accessible and/or could you elaborate on the "some limitation"
>>>> >> comment?
>>>> > 9125 spec is publicly accessible.
>>> If you can't see the pic, please open the attachment. Thanks!
>>
>> Neither Bjorn nor myself could see the pic (from the previous thread
>> or this thread's attachment).
>>
>>>
>>>
>
> Just an FYI that I proposed a different tact at
> https://lkml.org/lkml/2013/3/16/168. For those following this thread
> you may want to start following that thread also.

I posted a third approach last night. For those of you following this
thread there are now three streams:
This stream,
https://lkml.org/lkml/2013/3/16/168 (which is also on the linux-pci list),
and https://lkml.org/lkml/2013/3/21/12 (which is also on the linux-pci list).

Perhaps the third time will be a charm