From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752938AbcGCTMR (ORCPT ); Sun, 3 Jul 2016 15:12:17 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:33868 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752835AbcGCTMQ (ORCPT ); Sun, 3 Jul 2016 15:12:16 -0400 Subject: Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 To: honghui.zhang@mediatek.com, joro@8bytes.org, treding@nvidia.com, mark.rutland@arm.com, robh@kernel.org, robin.murphy@arm.com References: <1465379461-14757-1-git-send-email-honghui.zhang@mediatek.com> <1465379461-14757-6-git-send-email-honghui.zhang@mediatek.com> <09eaf7a5-2b18-1ea6-5699-2e968c6b79a4@gmail.com> Cc: p.zabel@pengutronix.de, devicetree@vger.kernel.org, pebolle@tiscali.nl, kendrick.hsu@mediatek.com, arnd@arndb.de, srv_heupstream@mediatek.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, tfiga@google.com, iommu@lists.linux-foundation.org, robh+dt@kernel.org, djkurtz@google.com, kernel@pengutronix.de, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, l.stach@pengutronix.de, yingjoe.chen@mediatek.com, eddie.huang@mediatek.com, youlin.pei@mediatek.com, erin.lo@mediatek.com From: Matthias Brugger Message-ID: <51441f39-e5b5-2cce-63ab-47bd3cf298b3@gmail.com> Date: Sun, 3 Jul 2016 21:12:11 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <09eaf7a5-2b18-1ea6-5699-2e968c6b79a4@gmail.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/03/2016 08:24 AM, Matthias Brugger wrote: > > > On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote: >> From: Honghui Zhang >> >> Add the dtsi node of iommu and smi for mt2701. >> >> Signed-off-by: Honghui Zhang >> --- >> arch/arm/boot/dts/mt2701.dtsi | 51 >> +++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> > > Applied, Please resend the patch including the infracfg and mmsys node. Regards, Matthias > > Thanks. > >> diff --git a/arch/arm/boot/dts/mt2701.dtsi >> b/arch/arm/boot/dts/mt2701.dtsi >> index 42d5a37..363de0d 100644 >> --- a/arch/arm/boot/dts/mt2701.dtsi >> +++ b/arch/arm/boot/dts/mt2701.dtsi >> @@ -16,6 +16,7 @@ >> #include >> #include >> #include >> +#include >> #include "skeleton64.dtsi" >> #include "mt2701-pinfunc.h" >> >> @@ -160,6 +161,16 @@ >> clock-names = "system-clk", "rtc-clk"; >> }; >> >> + smi_common: smi@1000c000 { >> + compatible = "mediatek,mt2701-smi-common"; >> + reg = <0 0x1000c000 0 0x1000>; >> + clocks = <&infracfg CLK_INFRA_SMI>, >> + <&mmsys CLK_MM_SMI_COMMON>, >> + <&infracfg CLK_INFRA_SMI>; >> + clock-names = "apb", "smi", "async"; >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; >> + }; >> + >> sysirq: interrupt-controller@10200100 { >> compatible = "mediatek,mt2701-sysirq", >> "mediatek,mt6577-sysirq"; >> @@ -169,6 +180,16 @@ >> reg = <0 0x10200100 0 0x1c>; >> }; >> >> + iommu: mmsys_iommu@10205000 { >> + compatible = "mediatek,mt2701-m4u"; >> + reg = <0 0x10205000 0 0x1000>; >> + interrupts = ; >> + clocks = <&infracfg CLK_INFRA_M4U>; >> + clock-names = "bclk"; >> + mediatek,larbs = <&larb0 &larb1 &larb2>; >> + #iommu-cells = <1>; >> + }; >> + >> apmixedsys: syscon@10209000 { >> compatible = "mediatek,mt2701-apmixedsys", "syscon"; >> reg = <0 0x10209000 0 0x1000>; >> @@ -234,6 +255,16 @@ >> status = "disabled"; >> }; >> >> + larb0: larb@14010000 { >> + compatible = "mediatek,mt2701-smi-larb"; >> + reg = <0 0x14010000 0 0x1000>; >> + mediatek,smi = <&smi_common>; >> + clocks = <&mmsys CLK_MM_SMI_LARB0>, >> + <&mmsys CLK_MM_SMI_LARB0>; >> + clock-names = "apb", "smi"; >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; >> + }; >> + >> imgsys: syscon@15000000 { >> compatible = "mediatek,mt2701-imgsys", "syscon"; >> reg = <0 0x15000000 0 0x1000>; >> @@ -241,6 +272,16 @@ >> status = "disabled"; >> }; >> >> + larb2: larb@15001000 { >> + compatible = "mediatek,mt2701-smi-larb"; >> + reg = <0 0x15001000 0 0x1000>; >> + mediatek,smi = <&smi_common>; >> + clocks = <&imgsys CLK_IMG_SMI_COMM>, >> + <&imgsys CLK_IMG_SMI_COMM>; >> + clock-names = "apb", "smi"; >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; >> + }; >> + >> vdecsys: syscon@16000000 { >> compatible = "mediatek,mt2701-vdecsys", "syscon"; >> reg = <0 0x16000000 0 0x1000>; >> @@ -248,6 +289,16 @@ >> status = "disabled"; >> }; >> >> + larb1: larb@16010000 { >> + compatible = "mediatek,mt2701-smi-larb"; >> + reg = <0 0x16010000 0 0x1000>; >> + mediatek,smi = <&smi_common>; >> + clocks = <&vdecsys CLK_VDEC_CKGEN>, >> + <&vdecsys CLK_VDEC_LARB>; >> + clock-names = "apb", "smi"; >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; >> + }; >> + >> hifsys: syscon@1a000000 { >> compatible = "mediatek,mt2701-hifsys", "syscon"; >> reg = <0 0x1a000000 0 0x1000>; >>