From: Dave Jiang <dave.jiang@intel.com>
To: Dan Williams <djbw@fb.com>
Cc: vinod.koul@intel.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 06/10] ioatdma: Removing PQ val disable for cb3.3
Date: Fri, 29 Mar 2013 10:31:10 -0700 [thread overview]
Message-ID: <5155CFDE.2070703@intel.com> (raw)
In-Reply-To: <CAA9_cmcAwp0g+ybe14Poxdi-7V=USbO8OCJJ++V1Dn0PUHKRKg@mail.gmail.com>
On 03/27/2013 11:48 AM, Dan Williams wrote:
> On Tue, Mar 26, 2013 at 3:43 PM, Dave Jiang <dave.jiang@intel.com> wrote:
>> The PQ Val ops work on the newer hardware so we should actually provide support
>> for it and remove the disabling bits.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>> drivers/dma/Kconfig | 2 -
>> drivers/dma/ioat/dma.h | 1
>> drivers/dma/ioat/dma_v3.c | 134 ++++++++++++++++++++++++++++++++++++++----
>> drivers/dma/ioat/registers.h | 2 +
>> 4 files changed, 125 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
>> index 80b6997..dec088d 100644
>> --- a/drivers/dma/Kconfig
>> +++ b/drivers/dma/Kconfig
>> @@ -63,8 +63,6 @@ config INTEL_IOATDMA
>> depends on PCI && X86
>> select DMA_ENGINE
>> select DCA
>> - select ASYNC_TX_DISABLE_PQ_VAL_DMA
>> - select ASYNC_TX_DISABLE_XOR_VAL_DMA
>> help
>> Enable support for the Intel(R) I/OAT DMA engine present
>> in recent Intel Xeon chipsets.
> [..]
>> @@ -1469,15 +1581,13 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca)
>> device->cleanup_fn = ioat3_cleanup_event;
>> device->timer_fn = ioat3_timer_event;
>>
>> - #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
>> - dma_cap_clear(DMA_PQ_VAL, dma->cap_mask);
>> - dma->device_prep_dma_pq_val = NULL;
>> - #endif
>> + if (is_xeon_cb32(pdev)) {
>> + dma_cap_clear(DMA_XOR_VAL, dma->cap_mask);
>> + dma->device_prep_dma_xor_val = NULL;
>>
>> - #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
>> - dma_cap_clear(DMA_XOR_VAL, dma->cap_mask);
>> - dma->device_prep_dma_xor_val = NULL;
>> - #endif
>> + dma_cap_clear(DMA_PQ_VAL, dma->cap_mask);
>> + dma->device_prep_dma_pq_val = NULL;
>> + }
> Note that this effectively disables raid offload for is_xeon_cb32()
> platforms since DMA_ASYNC_TX will not be set.
We are ok with that until a workaround can be figured out.
next prev parent reply other threads:[~2013-03-29 17:31 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-26 22:42 [PATCH 00/10] Add Intel Atom S1200 seris ioatdma support Dave Jiang
2013-03-26 22:42 ` [PATCH 01/10] ioatdma: Adding PCI IDs for Intel Atom S1200 product family ioatdma devices Dave Jiang
2013-03-26 22:42 ` [PATCH 02/10] ioatdma: Add 64bit chansts register read for ioat v3.3 Dave Jiang
2013-03-26 22:42 ` [PATCH 03/10] ioatdma: channel reset scheme fixup on Intel Atom S1200 platforms Dave Jiang
2013-03-26 22:42 ` [PATCH 04/10] ioatdma: Removing hw bug workaround for CB3.x .2 and earlier Dave Jiang
2013-03-26 22:42 ` [PATCH 05/10] ioatdma: skip legacy reset bits since v3.3 plattform doesn't need it Dave Jiang
2013-03-26 22:43 ` [PATCH 06/10] ioatdma: Removing PQ val disable for cb3.3 Dave Jiang
2013-03-27 18:48 ` Dan Williams
2013-03-29 17:31 ` Dave Jiang [this message]
2013-03-26 22:43 ` [PATCH 07/10] ioatdma: skip silicon bug workaround for pq_align " Dave Jiang
2013-03-26 22:43 ` [PATCH 08/10] ioatdma: Adding support for 16 src PQ ops and super extended descriptors Dave Jiang
2013-03-26 22:43 ` [PATCH 09/10] ioatdma: Adding write back descriptor error status support for ioatdma 3.3 Dave Jiang
2013-03-26 23:47 ` Dan Williams
2013-03-26 23:55 ` Dave Jiang
2013-03-28 22:25 ` [PATCH 09/10 v2] " Jiang, Dave
2013-03-26 22:43 ` [PATCH 10/10] ioatdma: S1200 platforms ioatdma channel 2 and 3 falsely advertise RAID cap Dave Jiang
2013-04-09 7:28 ` [PATCH 00/10] Add Intel Atom S1200 seris ioatdma support Vinod Koul
2013-04-10 0:56 ` Dan Williams
[not found] ` <CAA9_cmftcvYN_g0Sj12tMa4T8LxbPdk6wDxwkbTrgQPUUfc0FA@mail.gmail.com>
2013-04-10 5:00 ` Vinod Koul
2013-04-10 5:10 ` Vinod Koul
2013-04-10 5:33 ` Jiang, Dave
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