Re: [PATCH 1/1] iommu/vt-d: Disallow dirty tracking if incoherent page walk

[Baolu Lu <baolu.lu@linux.intel.com>]

On 9/24/25 20:04, Jason Gunthorpe wrote:
> On Wed, Sep 24, 2025 at 04:34:46PM +0800, Lu Baolu wrote:
>> Dirty page tracking relies on the IOMMU atomically updating the dirty bit
>> in the paging-structure entry. For this operation to succeed, the paging-
>> structure memory must be coherent between the IOMMU and the CPU. In
>> another word, if the iommu page walk is incoherent, dirty page tracking
>> doesn't work.
>>
>> The Intel VT-d specification, Section 3.10 "Snoop Behavior" states:
>>
>> "Remapping hardware encountering the need to atomically update A/EA/D bits
>>   in a paging-structure entry that is not snooped will result in a non-
>>   recoverable fault."
>>
>> To prevent an IOMMU from being incorrectly configured for dirty page
>> tracking when it is operating in an incoherent mode, mark SSADS as
>> supported only when both ecap_slads and ecap_smpwc are supported.
>>
>> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>
>> ---
>>   drivers/iommu/intel/iommu.h | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
> Reviewed-by: Jason Gunthorpe<jgg@nvidia.com>

Thank you!

> Basically due to the above spec the IOMMU implementation would be
> invalid to set slads and !smpwc ?

I suppose so.

But even if smpwc is set to 1, software could still configure an
incoherent page walk by clearing the Page Walk Snoop bit in the PASID
entry. (The current Intel IOMMU driver always sets that bit as long as
the capability exists). In that case, the hardware might encounter the
situation mentioned above.

Thanks,
baolu