From: Dave Hansen <dave@sr71.net>
To: HATAYAMA Daisuke <d.hatayama@jp.fujitsu.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>,
"kexec@lists.infradead.org" <kexec@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Cliff Wickman <cpw@sgi.com>, Simon Horman <horms@verge.net.au>,
"Eric W. Biederman" <ebiederm@xmission.com>,
Yinghai Lu <yinghai@kernel.org>, Thomas Renninger <trenn@suse.de>,
Vivek Goyal <vgoyal@redhat.com>
Subject: Re: [PATCH 5/5] kexec: X86: Pass memory ranges via e820 table instead of memmap= boot parameter
Date: Sun, 14 Apr 2013 22:58:44 -0700 [thread overview]
Message-ID: <516B9714.80007@sr71.net> (raw)
In-Reply-To: <516B87A6.9080708@jp.fujitsu.com>
On 04/14/2013 09:52 PM, HATAYAMA Daisuke wrote:
> This sounds like there's no such issue on x86 cache mechanism. Is it
> correct? If so, what is the difference between ia64 and x86 cache
> mechanisms?
I'm just going by the code comments:
drivers/char/mem.c
> /*
> * On ia64 if a page has been mapped somewhere as uncached, then
> * it must also be accessed uncached by the kernel or data
> * corruption may occur.
> */
next prev parent reply other threads:[~2013-04-15 5:57 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1365683207-42425-1-git-send-email-trenn@suse.de>
[not found] ` <1365683207-42425-6-git-send-email-trenn@suse.de>
2013-04-11 14:55 ` [PATCH 5/5] kexec: X86: Pass memory ranges via e820 table instead of memmap= boot parameter Yinghai Lu
2013-04-11 15:06 ` H. Peter Anvin
2013-04-12 14:31 ` Vivek Goyal
2013-04-12 14:56 ` H. Peter Anvin
2013-04-12 22:17 ` Dave Hansen
2013-04-12 23:17 ` H. Peter Anvin
2013-04-15 4:52 ` HATAYAMA Daisuke
2013-04-15 5:58 ` Dave Hansen [this message]
2013-04-15 7:58 ` HATAYAMA Daisuke
2013-04-15 14:49 ` H. Peter Anvin
2013-04-12 12:24 ` Thomas Renninger
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