Re: [PATCH] clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocks

[Sylwester Nawrocki <s.nawrocki@samsung.com>]

On 05/10/2013 06:38 PM, Sylwester Nawrocki wrote:
> Currently no driver *) handles the sysreg clock, with an assumption
> that this clock is always left in its default state (enabled).
> 
> Before commit 6e6aac7590f902d14d90bace3fd499
> ARM: EXYNOS: Migrate clock support to common clock framework
> 
> the sysreg clock was not even defined and hence wasn't handled
> explicitly in the kernel.
> 
> To restore the previous behaviour disable masking the sysreg clock
> off in the clock core by default.
> 
> *) Except the Exynos4x12 FIMC-IS driver, which will be modified
>    to not touch the sysreg clock.
> 
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Mike,

would you consider applying it as a bug fix for v3.10-rc ?

I'd like to queue patch [1] for 3.10 through the media tree,
once $subject patch is in Linus' tree.

Thanks,
Sylwester

[1] https://patchwork.linuxtv.org/patch/18374

> ---
>  drivers/clk/samsung/clk-exynos4.c |    6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 070bbeb..0f2f5e5 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -797,7 +797,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
>  	GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
>  	GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
>  	GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
> -	GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
> +	GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
> +			CLK_IGNORE_UNUSED, 0),
>  	GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
>  	GATE(smmu_rotator, "smmu_rotator", "aclk200",
>  			E4210_GATE_IP_IMAGE, 4, 0, 0),
> @@ -826,7 +827,8 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
>  	GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
>  	GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
>  	GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
> -	GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
> +	GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
> +			CLK_IGNORE_UNUSED, 0),
>  	GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
>  	GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
>  			SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
> --
> 1.7.9.5