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Message-ID: <51FB99FF.9080003@monstr.eu>
Date: Fri, 02 Aug 2013 13:37:35 +0200
From: Michal Simek <monstr@monstr.eu>
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To: Soren Brinkmann <soren.brinkmann@xilinx.com>
CC: Rob Herring <rob.herring@calxeda.com>, Pawel Moll <pawel.moll@arm.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Stephen Warren <swarren@wwwdotorg.org>,
        Ian Campbell <ian.campbell@citrix.com>,
        Russell King <linux@arm.linux.org.uk>,
        Michal Simek <michal.simek@xilinx.com>, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH] arm: zynq: dt: Set correct L2 ram latencies
References: <1375313099-8402-1-git-send-email-soren.brinkmann@xilinx.com>
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On 08/01/2013 01:24 AM, Soren Brinkmann wrote:
> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
> ---
>  arch/arm/boot/dts/zynq-7000.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>=20
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-=
7000.dtsi
> index 6f54a64..e32b92b 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -41,8 +41,8 @@
>  		L2: cache-controller {
>  			compatible =3D "arm,pl310-cache";
>  			reg =3D <0xF8F02000 0x1000>;
> -			arm,data-latency =3D <2 3 2>;
> -			arm,tag-latency =3D <2 3 2>;
> +			arm,data-latency =3D <3 2 2>;
> +			arm,tag-latency =3D <2 2 2>;
>  			cache-unified;
>  			cache-level =3D <2>;
>  		};
>=20

Applied to zynq/dt.

Thanks,
Michal

--=20
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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