From: Michal Simek <monstr@monstr.eu>
To: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Jason Cooper <jason@lakedaemon.net>,
Michal Simek <michal.simek@xilinx.com>,
linux-kernel@vger.kernel.org, Alan Tull <atull@altera.com>,
Pavel Machek <pavel@ucw.cz>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Dinh Nguyen <dinguyen@altera.com>,
Philip Balister <philip@balister.org>,
Alessandro Rubini <rubini@gnudd.com>,
Mauro Carvalho Chehab <m.chehab@samsung.com>,
Andrew Morton <akpm@linux-foundation.org>,
Cesar Eduardo Barros <cesarb@cesarb.net>,
Joe Perches <joe@perches.com>,
"David S. Miller" <davem@davemloft.net>,
Stephen Warren <swarren@nvidia.com>,
Arnd Bergmann <arnd@arndb.de>,
David Brown <davidb@codeaurora.org>,
Dom Cobley <popcornmix@gmail.com>
Subject: Re: [RFC PATCH] fpga: Introduce new fpga subsystem
Date: Fri, 27 Sep 2013 15:31:53 +0200 [thread overview]
Message-ID: <524588C9.1090600@monstr.eu> (raw)
In-Reply-To: <20130918203247.GA11181@obsidianresearch.com>
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Hi Jason,
On 09/18/2013 10:32 PM, Jason Gunthorpe wrote:
> On Wed, Sep 18, 2013 at 03:15:17PM -0400, Jason Cooper wrote:
>
>> + Jason Gunthorpe
>
> Thanks, looks interesting, we could possibly use this interface if it
> met our needs..
>
>> On Wed, Sep 18, 2013 at 05:56:39PM +0200, Michal Simek wrote:
>>> This new subsystem should unify all fpga drivers which
>>> do the same things. Load configuration data to fpga
>>> or another programmable logic through common interface.
>>> It doesn't matter if it is MMIO device, gpio bitbanging,
>>> etc. connection. The point is to have the same
>>> inteface for these drivers.
>
> So, we have many years of in-field experience with this and this API
> doesn't really match what we do.
>
> Here are the steps we perform, from userspace:
> - Ask kernel to place FPGA into reset and prepare for programming
> * Kernel can return an error (eg FPGA failed to erase, etc)
> * this is the PROG_N low -> DONE high, PROG_N high -> INIT_N high
> sequencing on Xilinx chips
> - Ask kernel to load a bitstream.
> * Userspace locats the bitstream file to load, and the mmaps it.
> * Userspace passes the entire file in a single write() call to the
> kernel which streams it over the configuration bus
> * The kernel can report an erro rhere (eg Xilinx can report CRC
> error)
> - Ask the kernel to verify that configuration is complete.
> * On Xilinx this wait for done to go high
> - Ask the kernel to release the configuration bus (tristate
> all drivers) (or sometimes we have to drive the bus low,
> it depends on the bitfile, user space knows what to do)
>
> It is very important that userspace know exactly which step fails
> because the resolution is different. We use this in a manufacturing
> setting, so failures are expected and need quick root cause
> determination.
>
> You could probably address that need by very clearly defining a
> variety of errno values for the various cases. However, it would be a
> disaster if every driver did something a little different :|
>
> Using request_firmware exclusively is not useful for us. We
> format the bitfile with a header that contains our internal tracking
> information. Sometimes we need to bitswap the bitfile. Our userspace
> handles all of this and can pass a bitfile in memory to write().
>
> request_firmware would be horrible to use :)
>
> Our API uses a binary sysfs attribute to stream the FPGA data, you
> might want to consider that.
I have done some experiments with binary sysfs attribute and can
you please be more specific how you are working with it?
I expect that you are detecting/specifying in the driver which
fpga is connected and you also need to know size of this device.
Then your driver allocate buffer with this size in the kernel
and streming data to this buffer. When this is done you are
using another sysfs files to control device programming.
Can you please correct me if I am wrong?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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next prev parent reply other threads:[~2013-09-27 13:32 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-18 15:56 [RFC PATCH 0/1] FPGA subsystem core Michal Simek
2013-09-18 15:56 ` [RFC PATCH] fpga: Introduce new fpga subsystem Michal Simek
2013-09-18 16:11 ` Joe Perches
2013-09-19 10:01 ` Michal Simek
2013-09-19 16:26 ` Alan Tull
2013-09-18 19:02 ` Dinh Nguyen
2013-09-19 11:53 ` Michal Simek
2013-09-18 19:15 ` Jason Cooper
2013-09-18 20:32 ` Jason Gunthorpe
2013-09-18 21:17 ` Alan Tull
2013-09-19 10:08 ` Pavel Machek
2013-09-19 11:02 ` Michal Simek
2013-09-20 20:55 ` Alan Tull
2013-09-24 15:55 ` Alan Tull
2013-09-24 15:58 ` Michal Simek
2013-09-24 16:22 ` Alan Tull
2013-09-24 22:18 ` Greg Kroah-Hartman
2013-09-25 13:55 ` Yves Vandervennet
2013-09-25 14:51 ` Michal Simek
2013-09-25 18:50 ` Alan Tull
2013-09-24 22:54 ` H. Peter Anvin
2013-09-25 10:41 ` Michal Simek
2013-09-25 12:00 ` Pavel Machek
2013-09-25 14:27 ` Philip Balister
2013-09-25 14:43 ` Michal Simek
2013-09-25 19:21 ` Alan Tull
2013-09-19 10:55 ` Michal Simek
2013-09-19 11:17 ` Pavel Machek
2013-09-19 11:22 ` Michal Simek
2013-09-19 12:52 ` /sys rules " Pavel Machek
2013-09-19 14:06 ` Greg KH
2013-09-19 14:10 ` Michal Simek
2013-09-19 14:18 ` Greg KH
2013-09-19 15:14 ` Alan Tull
2013-09-19 14:20 ` Jason Cooper
2013-09-19 14:37 ` Greg KH
2013-09-19 22:48 ` Pavel Machek
[not found] ` <CADuitaA3PLaOgmqXzfMdMDaXg7G6bT-DufjcuhtWfvaoWRj__Q@mail.gmail.com>
2013-09-19 15:14 ` Michal Simek
2013-09-19 15:18 ` Yves Vandervennet
2013-09-19 17:28 ` Jason Gunthorpe
2013-09-23 13:10 ` Michal Simek
2013-09-23 17:10 ` Jason Gunthorpe
2013-09-25 10:48 ` Michal Simek
2013-09-23 13:02 ` Michal Simek
2013-09-19 10:03 ` Pavel Machek
2013-09-19 10:45 ` Michal Simek
2013-09-27 13:31 ` Michal Simek [this message]
2013-09-30 17:12 ` Jason Gunthorpe
2013-10-01 15:59 ` Michal Simek
2013-09-18 23:45 ` Ryan Mallon
2013-09-19 11:37 ` Michal Simek
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