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Date: Sun, 24 Nov 2013 19:10:58 +0100
From: christophe leroy <christophe.leroy@c-s.fr>
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To: Peter Zijlstra <a.p.zijlstra@chello.nl>, Paul Mackerras <paulus@samba.org>,
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CC: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: perf events: how to implement TLB misses as SW event ?
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Today in the perfevents subsystem it looks like DTLB/ITLB misses are 
implemented as HW counter only.
On some processors, like PowerPC 8xx, there is no counter for that. 
However DTLB/ITLB misses are handled as exceptions via software, so we 
have an opportunity to implement a SW counter for that.
What's the easiest/best way to implement it ?

Christophe