* [PATCH] clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks
@ 2013-11-26 16:48 Peter De Schrijver
2013-11-26 20:07 ` Stephen Warren
0 siblings, 1 reply; 3+ messages in thread
From: Peter De Schrijver @ 2013-11-26 16:48 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Prashant Gaikwad, Mike Turquette, Stephen Warren, Thierry Reding,
linux-arm-kernel, linux-tegra, linux-kernel
Perform upwards rounding when calculating dividers for periph clks on Tegra30
and Tegra114.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra114.c | 53 ++++++++++++++++++++-----------------
drivers/clk/tegra/clk-tegra30.c | 19 +++++++------
2 files changed, 39 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 7661128..e390492 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -791,50 +791,53 @@ static unsigned long tegra114_input_freq[] = {
#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _regs, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
- 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
- periph_clk_enb_refcnt, _gate_flags, _clk_id, \
- _parents##_idx, 0)
+ 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
+ _regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\
+ _clk_id, _parents##_idx, 0)
#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
_clk_num, _regs, _gate_flags, _clk_id, flags)\
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
- 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
- periph_clk_enb_refcnt, _gate_flags, _clk_id, \
- _parents##_idx, flags)
+ 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
+ _regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\
+ _clk_id, _parents##_idx, flags)
#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _regs, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
- 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \
- periph_clk_enb_refcnt, _gate_flags, _clk_id, \
- _parents##_idx, 0)
+ 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
+ _regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\
+ _clk_id, _parents##_idx, 0)
#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
_clk_num, _regs, _gate_flags, _clk_id, flags)\
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
- 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
- _clk_num, periph_clk_enb_refcnt, _gate_flags, \
- _clk_id, _parents##_idx, flags)
+ 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
+ TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
+ periph_clk_enb_refcnt, _gate_flags, _clk_id, \
+ _parents##_idx, flags)
#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
_clk_num, _regs, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
- 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
- _clk_num, periph_clk_enb_refcnt, _gate_flags, \
- _clk_id, _parents##_idx, 0)
+ 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
+ TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
+ periph_clk_enb_refcnt, _gate_flags, _clk_id, \
+ _parents##_idx, 0)
#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
_clk_num, _regs, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
- 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
- _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \
- _parents##_idx, 0)
+ 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART | \
+ TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
+ periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
_clk_num, _regs, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
- 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \
- periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
+ 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
+ _regs, _clk_num, periph_clk_enb_refcnt, 0, _clk_id,\
+ _parents##_idx, 0)
#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
_mux_shift, _mux_mask, _clk_num, _regs, \
@@ -847,14 +850,16 @@ static unsigned long tegra114_input_freq[] = {
#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _regs, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
- 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
- _clk_num, periph_clk_enb_refcnt, _gate_flags, \
- _clk_id, _parents##_idx, 0)
+ 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
+ TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
+ periph_clk_enb_refcnt, _gate_flags, _clk_id, \
+ _parents##_idx, 0)
#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\
_regs, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
- _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
+ _offset, 16, 0xE01F, 0, 0, 8, 1, \
+ TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
periph_clk_enb_refcnt, _gate_flags , _clk_id, \
mux_d_audio_clk_idx, 0)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index dbe7c80..147f5b9 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -282,8 +282,8 @@ static DEFINE_SPINLOCK(sysrate_lock);
#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _regs, _gate_flags, _clk_id) \
TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
- 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \
- periph_clk_enb_refcnt, _gate_flags, _clk_id)
+ 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, _regs, \
+ _clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id)
#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _regs, _gate_flags, _clk_id) \
@@ -295,21 +295,22 @@ static DEFINE_SPINLOCK(sysrate_lock);
#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _regs, _gate_flags, _clk_id) \
TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
- 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \
- periph_clk_enb_refcnt, _gate_flags, _clk_id)
+ 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, _regs,\
+ _clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id)
#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _regs, _gate_flags, _clk_id) \
TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
- 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
- _clk_num, periph_clk_enb_refcnt, _gate_flags, \
- _clk_id)
+ 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
+ TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
+ periph_clk_enb_refcnt, _gate_flags, _clk_id)
#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
_clk_num, _regs, _clk_id) \
TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
- 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \
- _clk_num, periph_clk_enb_refcnt, 0, _clk_id)
+ 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART | \
+ TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
+ periph_clk_enb_refcnt, 0, _clk_id)
#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
_mux_shift, _mux_width, _clk_num, _regs, \
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks
2013-11-26 16:48 [PATCH] clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks Peter De Schrijver
@ 2013-11-26 20:07 ` Stephen Warren
2013-11-28 14:09 ` Peter De Schrijver
0 siblings, 1 reply; 3+ messages in thread
From: Stephen Warren @ 2013-11-26 20:07 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Prashant Gaikwad, Mike Turquette, Thierry Reding,
linux-arm-kernel, linux-tegra, linux-kernel
On 11/26/2013 09:48 AM, Peter De Schrijver wrote:
> Perform upwards rounding when calculating dividers for periph clks on Tegra30
> and Tegra114.
Tested-by: Stephen Warren <swarren@nvidia.com>
I tested audio and SPI on Dalmore and Beaver, using the following branch
which has this commit integrated:
git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-rework-1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks
2013-11-26 20:07 ` Stephen Warren
@ 2013-11-28 14:09 ` Peter De Schrijver
0 siblings, 0 replies; 3+ messages in thread
From: Peter De Schrijver @ 2013-11-28 14:09 UTC (permalink / raw)
To: Stephen Warren
Cc: Prashant Gaikwad, Mike Turquette, Thierry Reding,
linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
On Tue, Nov 26, 2013 at 09:07:31PM +0100, Stephen Warren wrote:
> On 11/26/2013 09:48 AM, Peter De Schrijver wrote:
> > Perform upwards rounding when calculating dividers for periph clks on Tegra30
> > and Tegra114.
>
> Tested-by: Stephen Warren <swarren@nvidia.com>
>
> I tested audio and SPI on Dalmore and Beaver, using the following branch
> which has this commit integrated:
> git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-rework-1
Merged into clk-tegra-next
^ permalink raw reply [flat|nested] 3+ messages in thread
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2013-11-26 16:48 [PATCH] clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks Peter De Schrijver
2013-11-26 20:07 ` Stephen Warren
2013-11-28 14:09 ` Peter De Schrijver
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