From: Florian Meier <florian.meier@koalo.de>
To: Daniel Matuschek <daniel@matuschek.net>, alsa-devel@alsa-project.org
Cc: Dimitris.Papastamos@wolfsonmicro.com, lgirdwood@gmail.com,
broonie@kernel.org, perex@perex.cz, tiwai@suse.de,
patches@opensource.wolfsonmicro.com,
linux-kernel@vger.kernel.org, info@crazy-audio.com
Subject: Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation
Date: Mon, 13 Jan 2014 10:21:47 +0100 [thread overview]
Message-ID: <52D3B02B.8070408@koalo.de> (raw)
In-Reply-To: <alpine.DEB.2.02.1401122206520.7929@parallels-Parallels-Virtual-Platform>
On 01/12/2014 10:11 PM, Daniel Matuschek wrote:
> Signed-off-by: Daniel Matuschek <daniel@matuschek.net>
>
> After some discussions of the patch last week, here is a new version.
> Simply reducing the post_table did not work, as for some frequencies
> both settings (MCLKDIV=0 and MCLKDIV=1) are needed (e.g. 96 and 192kHz)
>
>
> WM8804 can run with PLL frequencies of 256xfs and 128xfs for
> most sample rates. At 192kHz only 128xfs is supported. The
> existing driver selects 128xfs automatically for some lower
> samples rates. By using an additional mclk_div divider, is
> is now possible to control the behaviour. This allows using
> 256xfs PLL frequency on all sample rates up to 96kHz. It
> should allow lower jitter and better signal quality. The
> behavior has to be controlled by the sound card driver,
> because some sample frequency share the same setting. e.g.
> 192kHz and 96kHz use 24.576MHz master clock. The only
> difference is the MCLK divider.
>
> ---
> sound/soc/codecs/wm8804.c | 17 ++++++++++++++---
> sound/soc/codecs/wm8804.h | 4 ++++
> 2 files changed, 18 insertions(+), 3 deletions(-)
You have disarranged the parts, again. It should be
WM8804 can run with PLL frequencies of 256xfs and 128xfs for
most sample rates. At 192kHz only 128xfs is supported. The
existing driver selects 128xfs automatically for some lower
samples rates. By using an additional mclk_div divider, is
is now possible to control the behaviour. This allows using
256xfs PLL frequency on all sample rates up to 96kHz. It
should allow lower jitter and better signal quality. The
behavior has to be controlled by the sound card driver,
because some sample frequency share the same setting. e.g.
192kHz and 96kHz use 24.576MHz master clock. The only
difference is the MCLK divider.
Signed-off-by: Daniel Matuschek <daniel@matuschek.net>
---
After some discussions of the patch last week, here is a new version.
Simply reducing the post_table did not work, as for some frequencies
both settings (MCLKDIV=0 and MCLKDIV=1) are needed (e.g. 96 and 192kHz)
sound/soc/codecs/wm8804.c | 17 ++++++++++++++---
sound/soc/codecs/wm8804.h | 4 ++++
2 files changed, 18 insertions(+), 3 deletions(-)
next prev parent reply other threads:[~2014-01-13 9:22 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-12 21:11 [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation Daniel Matuschek
2014-01-13 9:21 ` Florian Meier [this message]
2014-01-13 11:14 ` Charles Keepax
-- strict thread matches above, loose matches on Subject: below --
2014-01-14 19:34 Daniel Matuschek
2014-01-17 0:54 ` Mark Brown
2014-01-17 10:35 ` Dimitris Papastamos
2014-01-17 9:48 ` Charles Keepax
2014-01-17 12:22 ` Mark Brown
2014-01-17 16:43 ` Florian Meier
2014-01-17 17:59 ` Mark Brown
2014-01-17 18:26 ` Daniel Matuschek
[not found] ` <52D97120.8030606@koalo.de>
[not found] ` <20140117183332.GC17314@sirena.org.uk>
2014-01-17 18:44 ` Florian Meier
2014-01-17 18:47 ` Mark Brown
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