Re: AMD 8131 and MSI quirk

[Roland Dreier <rolandd@cisco.com>]

    Matthew> Perhaps the right thing to do is to change pad2 (in
    Matthew> struct pci_bus) to bus_flags and make bit 0
    Matthew> PCI_BRIDGE_FLAGS_NO_MSI ?

Seems reasonable, but I'm still not sure how to implement this.  Where
does this bit get set and propagated to secondary buses?

To give a somewhat pathological real-world example, Mellanox PCI-X
adapters have a PCI bridge in them; in other words, a single adapter
looks like:

	0000:03:01.0 PCI bridge: Mellanox Technologies MT23108 PCI Bridge (rev a1) (prog-if 00 [Normal decode])
		Flags: bus master, 66MHz, medium devsel, latency 64
		Bus: primary=03, secondary=04, subordinate=04, sec-latency=68
		Memory behind bridge: e8200000-e82fffff
		Prefetchable memory behind bridge: 00000000ea800000-00000000f7f00000
		Capabilities: [70] PCI-X bridge device.
	
	0000:04:00.0 InfiniBand: Mellanox Technologies MT23108 InfiniHost (rev a1)
		Subsystem: Mellanox Technologies MT23108 InfiniHost
		Flags: bus master, fast Back2Back, 66MHz, medium devsel, latency 64, IRQ 185
		Memory at e8200000 (64-bit, non-prefetchable) [size=1M]
		Memory at ea800000 (64-bit, prefetchable) [size=8M]
		Memory at f0000000 (64-bit, prefetchable) [size=128M]
		Capabilities: [40] #11 [001f]
		Capabilities: [50] Vital Product Data
		Capabilities: [60] Message Signalled Interrupts: 64bit+ Queue=0/5 Enable-
		Capabilities: [70] PCI-X non-bridge device.

That means the NO_MSI flag still needs to get propagated from the 8131
bridge to the Mellanox bridge, and that needs to cause no_msi to get
set on the actual device.

Also, if someone hot-plugged such an adapter into a bus below an AMD
8131 host bridge (I believe eg Sun V40Zs have hot-pluggable slots like
that), then the NO_MSI flag still needs to get propagated from the
8131 bridge to the Mellanox bridge and set no_msi on the final device.

Where in the PCI driver code is the right place to handle all this (I
hope by writing the code only once)?

 - R.