[PATCH V4 1/4] ARM: shmobile: r8a7791: Add USBHS clock support

vladimir.barinov
2014-02-23T18:01:09Z

This adds USBHS clocks to the R8A7791 SoC.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

Changes in V4:
Changes in V3:
* none.

Changes in V2:
* capitalized ARM in the subject;
* rebased on top the latest devel tag.

---
arch/arm/mach-shmobile/clock-r8a7791.c | 4 ++++
1 file changed, 4 insertions(+)

Index: build/arch/arm/mach-shmobile/clock-r8a7791.c
===================================================================
--- build.orig/arch/arm/mach-shmobile/clock-r8a7791.c 2014-02-23 21:47:44.486571967 +0400
+++ build/arch/arm/mach-shmobile/clock-r8a7791.c 2014-02-23 21:47:52.582571801 +0400
@@ -177,6 +177,7 @@
MSTP811, MSTP810, MSTP809,
MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
MSTP719, MSTP718, MSTP715, MSTP714,
+ MSTP704,
MSTP522,
MSTP314, MSTP312, MSTP311,
MSTP216, MSTP207, MSTP206,
@@ -208,6 +209,7 @@
[MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */
[MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
[MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
+ [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
[MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
@@ -281,6 +283,8 @@
CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),
CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
+ CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
+ CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
};

#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \