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From: Boris BREZILLON <boris.brezillon@free-electrons.com>
To: "Emilio López" <emilio@elopez.com.ar>,
	"Randy Dunlap" <rdunlap@infradead.org>,
	"Maxime Ripard" <maxime.ripard@free-electrons.com>,
	"Mike Turquette" <mturquette@linaro.org>,
	"Linus Walleij" <linus.walleij@linaro.org>
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 07/15] ARM: sunxi: dt: define A31's APB0 clk gates node
Date: Wed, 09 Apr 2014 16:43:40 +0200	[thread overview]
Message-ID: <53455C9C.1040607@free-electrons.com> (raw)
In-Reply-To: <534553FF.4060401@elopez.com.ar>


On 09/04/2014 16:06, Emilio López wrote:
> Hi Boris,
>
> El 09/04/14 10:51, Boris BREZILLON escribió:
>> Define the APB0 clk gates controlled by the PRCM (Power/Reset/Clock
>> Management) block.
>>
>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>> ---
>>   arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
>> b/arch/arm/boot/dts/sun6i-a31.dtsi
>> index 3858424..61e8b34 100644
>> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
>> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
>> @@ -141,6 +141,16 @@
>>                       "ahb1_drc0", "ahb1_drc1";
>>           };
>>
>> +        apb0_gates: apb0_gates@01f01428 {
>
> Looks like this node is out of place, judging by the address. Try to
> keep them in order.

Sure, I'll fix it for the next version.

>
>> +            #clock-cells = <1>;
>> +            compatible = "allwinner,sun6i-a31-apb0-gates-clk";
>> +            reg = <0x01f01428 0x4>;
>> +            clock-output-names = "apb0_pio", "apb0_ir",
>> +                    "apb0_timer01", "apb0_p2wi",
>> +                    "apb0_uart", "apb0_1wire",
>> +                    "apb0_i2c";
>> +        };
>> +
>>           apb1: apb1@01c20054 {
>>               #clock-cells = <0>;
>>               compatible = "allwinner,sun4i-apb0-clk";
>>
>
> Cheers,
>
> Emilio

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


  reply	other threads:[~2014-04-09 14:43 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-09 13:51 [PATCH 00/15] ARM: sunxi: add A31 PL pins support Boris BREZILLON
2014-04-09 13:51 ` [PATCH 01/15] ARM: sunxi: dt: list all pinctrl compatible strings Boris BREZILLON
2014-04-09 14:43   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 02/15] ARM: sunxi: dt: document pinctrl clock related properties Boris BREZILLON
2014-04-09 14:45   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 03/15] ARM: sunxi: dt: add pinctrl clock-names properties Boris BREZILLON
2014-04-09 13:51 ` [PATCH 04/15] pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk Boris BREZILLON
2014-04-10 18:14   ` Linus Walleij
2014-04-10 18:16     ` Linus Walleij
2014-04-10 21:17       ` Boris BREZILLON
2014-04-09 13:51 ` [PATCH 05/15] clk: sunxi: add A31 APB0 clk gate defintions Boris BREZILLON
2014-04-09 14:49   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 06/15] clk: sunxi: add A31 APB0 gates compatible string to the documentation Boris BREZILLON
2014-04-09 13:59   ` Chen-Yu Tsai
2014-04-09 14:45     ` Boris BREZILLON
2014-04-09 14:51   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 07/15] ARM: sunxi: dt: define A31's APB0 clk gates node Boris BREZILLON
2014-04-09 14:06   ` Emilio López
2014-04-09 14:43     ` Boris BREZILLON [this message]
2014-04-09 15:08   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 08/15] reset: sunxi: document sunxi's reset controllers bindings Boris BREZILLON
2014-04-09 13:51 ` [PATCH 09/15] clk: sunxi: add A31 APB0 reset line defintions Boris BREZILLON
2014-04-09 13:51 ` [PATCH 10/15] pinctrl: sunxi: add PL pin definitions Boris BREZILLON
2014-04-09 13:51 ` [PATCH 11/15] pinctrl: sunxi: add support for A31 PL pins Boris BREZILLON
2014-04-09 13:51 ` [PATCH 12/15] pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC Boris BREZILLON
2014-04-09 15:33   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 13/15] pinctrl: sunxi: retrieve and enable PL reset line " Boris BREZILLON
2014-04-09 15:34   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 14/15] pinctrl: sunxi: define A31 PL0/PL1 pins Boris BREZILLON
2014-04-09 15:38   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 15/15] ARM: sunxi: dt: add support for A31's PL pins Boris BREZILLON
2014-04-09 14:53 ` [PATCH 00/15] ARM: sunxi: add A31 PL pins support Chen-Yu Tsai
2014-04-09 15:17   ` Maxime Ripard
2014-04-09 15:45     ` Maxime Ripard
2014-04-09 16:27     ` Chen-Yu Tsai
2014-04-10  8:10       ` Maxime Ripard
2014-04-10  9:56         ` Chen-Yu Tsai
2014-04-09 16:14   ` Boris BREZILLON
2014-04-09 17:14     ` Chen-Yu Tsai
2014-04-09 18:04       ` Boris BREZILLON
2014-04-10  8:16       ` Maxime Ripard

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