[PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Felipe Balbi]

Hi,

this series lets us access the newer registers introduced
back in OMAP4 which give us some valid information about
the OMAP HSMMC IP like max block size, support for ADMA,
support for Retention.

Right now, only setting max_blk_size correctly as supporting
ADMA and Retention will take a lot of work.

Tested on OMAP5 uEVM.

Felipe Balbi (5):
  mmc: host: omap_hsmmc: pass host as an argument
  mmc: host: omap_hsmmc: add reg_offset field
  mmc: host: omap_hsmmc: introduce new accessor functions
  mmc: host: omap_hsmmc: switch over to new accessors
  mmc: host: omap_hsmmc: set max_blk_size correctly

 drivers/mmc/host/omap_hsmmc.c | 291 ++++++++++++++++++++++++++----------------
 1 file changed, 182 insertions(+), 109 deletions(-)

-- 
1.9.1.286.g5172cb3

[PATCH 1/5] mmc: host: omap_hsmmc: pass host as an argument

[Felipe Balbi]

This patch is in preparation for a larger series
of cleanups on the omap_hsmmc.c driver.

In newer instances of this IP, there's a lot of
configuration details which we can grab by reading
some new registers which were prepended to the
address space.

Signed-off-by: Felipe Balbi <balbi@ti.com>
---
 drivers/mmc/host/omap_hsmmc.c | 198 +++++++++++++++++++++---------------------
 1 file changed, 99 insertions(+), 99 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index e91ee21..a8f1e08 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -151,11 +151,11 @@
 /*
  * MMC Host controller read/write API's
  */
-#define OMAP_HSMMC_READ(base, reg)	\
-	__raw_readl((base) + OMAP_HSMMC_##reg)
+#define OMAP_HSMMC_READ(host, reg)	\
+	__raw_readl((host)->base + OMAP_HSMMC_##reg)
 
-#define OMAP_HSMMC_WRITE(base, reg, val) \
-	__raw_writel((val), (base) + OMAP_HSMMC_##reg)
+#define OMAP_HSMMC_WRITE(host, reg, val) \
+	__raw_writel((val), (host)->base + OMAP_HSMMC_##reg)
 
 struct omap_hsmmc_next {
 	unsigned int	dma_len;
@@ -492,8 +492,8 @@ static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
  */
 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 {
-	OMAP_HSMMC_WRITE(host->base, SYSCTL,
-		OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
+	OMAP_HSMMC_WRITE(host, SYSCTL,
+		OMAP_HSMMC_READ(host, SYSCTL) | CEN);
 }
 
 /*
@@ -501,9 +501,9 @@ static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
  */
 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 {
-	OMAP_HSMMC_WRITE(host->base, SYSCTL,
-		OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
-	if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
+	OMAP_HSMMC_WRITE(host, SYSCTL,
+		OMAP_HSMMC_READ(host, SYSCTL) & ~CEN);
+	if ((OMAP_HSMMC_READ(host, SYSCTL) & CEN) != 0x0)
 		dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 }
 
@@ -521,16 +521,16 @@ static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 	if (cmd->opcode == MMC_ERASE)
 		irq_mask &= ~DTO_EN;
 
-	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
-	OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
-	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
+	OMAP_HSMMC_WRITE(host, STAT, STAT_CLEAR);
+	OMAP_HSMMC_WRITE(host, ISE, irq_mask);
+	OMAP_HSMMC_WRITE(host, IE, irq_mask);
 }
 
 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 {
-	OMAP_HSMMC_WRITE(host->base, ISE, 0);
-	OMAP_HSMMC_WRITE(host->base, IE, 0);
-	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
+	OMAP_HSMMC_WRITE(host, ISE, 0);
+	OMAP_HSMMC_WRITE(host, IE, 0);
+	OMAP_HSMMC_WRITE(host, STAT, STAT_CLEAR);
 }
 
 /* Calculate divisor for the given clock frequency */
@@ -558,17 +558,17 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 
 	omap_hsmmc_stop_clock(host);
 
-	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
+	regval = OMAP_HSMMC_READ(host, SYSCTL);
 	regval = regval & ~(CLKD_MASK | DTO_MASK);
 	clkdiv = calc_divisor(host, ios);
 	regval = regval | (clkdiv << 6) | (DTO << 16);
-	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
-	OMAP_HSMMC_WRITE(host->base, SYSCTL,
-		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
+	OMAP_HSMMC_WRITE(host, SYSCTL, regval);
+	OMAP_HSMMC_WRITE(host, SYSCTL,
+		OMAP_HSMMC_READ(host, SYSCTL) | ICE);
 
 	/* Wait till the ICS bit is set */
 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
-	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
+	while ((OMAP_HSMMC_READ(host, SYSCTL) & ICS) != ICS
 		&& time_before(jiffies, timeout))
 		cpu_relax();
 
@@ -583,14 +583,14 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 	 */
 	if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
 	    (ios->timing != MMC_TIMING_UHS_DDR50) &&
-	    ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
-		regval = OMAP_HSMMC_READ(host->base, HCTL);
+	    ((OMAP_HSMMC_READ(host, CAPA) & HSS) == HSS)) {
+		regval = OMAP_HSMMC_READ(host, HCTL);
 		if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 			regval |= HSPE;
 		else
 			regval &= ~HSPE;
 
-		OMAP_HSMMC_WRITE(host->base, HCTL, regval);
+		OMAP_HSMMC_WRITE(host, HCTL, regval);
 	}
 
 	omap_hsmmc_start_clock(host);
@@ -601,24 +601,24 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 	struct mmc_ios *ios = &host->mmc->ios;
 	u32 con;
 
-	con = OMAP_HSMMC_READ(host->base, CON);
+	con = OMAP_HSMMC_READ(host, CON);
 	if (ios->timing == MMC_TIMING_UHS_DDR50)
 		con |= DDR;	/* configure in DDR mode */
 	else
 		con &= ~DDR;
 	switch (ios->bus_width) {
 	case MMC_BUS_WIDTH_8:
-		OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
+		OMAP_HSMMC_WRITE(host, CON, con | DW8);
 		break;
 	case MMC_BUS_WIDTH_4:
-		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
-		OMAP_HSMMC_WRITE(host->base, HCTL,
-			OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
+		OMAP_HSMMC_WRITE(host, CON, con & ~DW8);
+		OMAP_HSMMC_WRITE(host, HCTL,
+			OMAP_HSMMC_READ(host, HCTL) | FOUR_BIT);
 		break;
 	case MMC_BUS_WIDTH_1:
-		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
-		OMAP_HSMMC_WRITE(host->base, HCTL,
-			OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
+		OMAP_HSMMC_WRITE(host, CON, con & ~DW8);
+		OMAP_HSMMC_WRITE(host, HCTL,
+			OMAP_HSMMC_READ(host, HCTL) & ~FOUR_BIT);
 		break;
 	}
 }
@@ -628,11 +628,11 @@ static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 	struct mmc_ios *ios = &host->mmc->ios;
 	u32 con;
 
-	con = OMAP_HSMMC_READ(host->base, CON);
+	con = OMAP_HSMMC_READ(host, CON);
 	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
-		OMAP_HSMMC_WRITE(host->base, CON, con | OD);
+		OMAP_HSMMC_WRITE(host, CON, con | OD);
 	else
-		OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
+		OMAP_HSMMC_WRITE(host, CON, con & ~OD);
 }
 
 #ifdef CONFIG_PM
@@ -647,10 +647,10 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 	u32 hctl, capa;
 	unsigned long timeout;
 
-	if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
-	    host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
-	    host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
-	    host->capa == OMAP_HSMMC_READ(host->base, CAPA))
+	if (host->con == OMAP_HSMMC_READ(host, CON) &&
+	    host->hctl == OMAP_HSMMC_READ(host, HCTL) &&
+	    host->sysctl == OMAP_HSMMC_READ(host, SYSCTL) &&
+	    host->capa == OMAP_HSMMC_READ(host, CAPA))
 		return 0;
 
 	host->context_loss++;
@@ -667,17 +667,17 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 		capa = VS18;
 	}
 
-	OMAP_HSMMC_WRITE(host->base, HCTL,
-			OMAP_HSMMC_READ(host->base, HCTL) | hctl);
+	OMAP_HSMMC_WRITE(host, HCTL,
+			OMAP_HSMMC_READ(host, HCTL) | hctl);
 
-	OMAP_HSMMC_WRITE(host->base, CAPA,
-			OMAP_HSMMC_READ(host->base, CAPA) | capa);
+	OMAP_HSMMC_WRITE(host, CAPA,
+			OMAP_HSMMC_READ(host, CAPA) | capa);
 
-	OMAP_HSMMC_WRITE(host->base, HCTL,
-			OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
+	OMAP_HSMMC_WRITE(host, HCTL,
+			OMAP_HSMMC_READ(host, HCTL) | SDBP);
 
 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
-	while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
+	while ((OMAP_HSMMC_READ(host, HCTL) & SDBP) != SDBP
 		&& time_before(jiffies, timeout))
 		;
 
@@ -704,10 +704,10 @@ out:
  */
 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 {
-	host->con =  OMAP_HSMMC_READ(host->base, CON);
-	host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
-	host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
-	host->capa = OMAP_HSMMC_READ(host->base, CAPA);
+	host->con =  OMAP_HSMMC_READ(host, CON);
+	host->hctl = OMAP_HSMMC_READ(host, HCTL);
+	host->sysctl =  OMAP_HSMMC_READ(host, SYSCTL);
+	host->capa = OMAP_HSMMC_READ(host, CAPA);
 }
 
 #else
@@ -737,20 +737,20 @@ static void send_init_stream(struct omap_hsmmc_host *host)
 
 	disable_irq(host->irq);
 
-	OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
-	OMAP_HSMMC_WRITE(host->base, CON,
-		OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
-	OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
+	OMAP_HSMMC_WRITE(host, IE, INT_EN_MASK);
+	OMAP_HSMMC_WRITE(host, CON,
+		OMAP_HSMMC_READ(host, CON) | INIT_STREAM);
+	OMAP_HSMMC_WRITE(host, CMD, INIT_STREAM_CMD);
 
 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 	while ((reg != CC_EN) && time_before(jiffies, timeout))
-		reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
+		reg = OMAP_HSMMC_READ(host, STAT) & CC_EN;
 
-	OMAP_HSMMC_WRITE(host->base, CON,
-		OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
+	OMAP_HSMMC_WRITE(host, CON,
+		OMAP_HSMMC_READ(host, CON) & ~INIT_STREAM);
 
-	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
-	OMAP_HSMMC_READ(host->base, STAT);
+	OMAP_HSMMC_WRITE(host, STAT, STAT_CLEAR);
+	OMAP_HSMMC_READ(host, STAT);
 
 	enable_irq(host->irq);
 }
@@ -829,7 +829,7 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 	if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
 	    host->mrq->sbc) {
 		cmdreg |= ACEN_ACMD23;
-		OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
+		OMAP_HSMMC_WRITE(host, SDMASA, host->mrq->sbc->arg);
 	}
 	if (data) {
 		cmdreg |= DP_SELECT | MSBS | BCE;
@@ -844,8 +844,8 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 
 	host->req_in_progress = 1;
 
-	OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
-	OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
+	OMAP_HSMMC_WRITE(host, ARG, cmd->arg);
+	OMAP_HSMMC_WRITE(host, CMD, cmdreg);
 }
 
 static int
@@ -933,13 +933,13 @@ omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 	if (cmd->flags & MMC_RSP_PRESENT) {
 		if (cmd->flags & MMC_RSP_136) {
 			/* response type 2 */
-			cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
-			cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
-			cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
-			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
+			cmd->resp[3] = OMAP_HSMMC_READ(host, RSP10);
+			cmd->resp[2] = OMAP_HSMMC_READ(host, RSP32);
+			cmd->resp[1] = OMAP_HSMMC_READ(host, RSP54);
+			cmd->resp[0] = OMAP_HSMMC_READ(host, RSP76);
 		} else {
 			/* response types 1, 1b, 3, 4, 5, 6 */
-			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
+			cmd->resp[0] = OMAP_HSMMC_READ(host, RSP10);
 		}
 	}
 	if ((host->data == NULL && !host->response_busy) || cmd->error)
@@ -1022,25 +1022,25 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 	unsigned long i = 0;
 	unsigned long limit = MMC_TIMEOUT_US;
 
-	OMAP_HSMMC_WRITE(host->base, SYSCTL,
-			 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
+	OMAP_HSMMC_WRITE(host, SYSCTL,
+			 OMAP_HSMMC_READ(host, SYSCTL) | bit);
 
 	/*
 	 * OMAP4 ES2 and greater has an updated reset logic.
 	 * Monitor a 0->1 transition first
 	 */
 	if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
-		while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
+		while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit))
 					&& (i++ < limit))
 			udelay(1);
 	}
 	i = 0;
 
-	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
+	while ((OMAP_HSMMC_READ(host, SYSCTL) & bit) &&
 		(i++ < limit))
 		udelay(1);
 
-	if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
+	if (OMAP_HSMMC_READ(host, SYSCTL) & bit)
 		dev_err(mmc_dev(host->mmc),
 			"Timeout waiting on controller reset in %s\n",
 			__func__);
@@ -1083,7 +1083,7 @@ static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 
 		if (status & ACE_EN) {
 			u32 ac12;
-			ac12 = OMAP_HSMMC_READ(host->base, AC12);
+			ac12 = OMAP_HSMMC_READ(host, AC12);
 			if (!(ac12 & ACNE) && host->mrq->sbc) {
 				end_cmd = 1;
 				if (ac12 & ACTO)
@@ -1101,7 +1101,7 @@ static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 		}
 	}
 
-	OMAP_HSMMC_WRITE(host->base, STAT, status);
+	OMAP_HSMMC_WRITE(host, STAT, status);
 	if (end_cmd || ((status & CC_EN) && host->cmd))
 		omap_hsmmc_cmd_done(host, host->cmd);
 	if ((end_trans || (status & TC_EN)) && host->mrq)
@@ -1116,12 +1116,12 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
 	struct omap_hsmmc_host *host = dev_id;
 	int status;
 
-	status = OMAP_HSMMC_READ(host->base, STAT);
+	status = OMAP_HSMMC_READ(host, STAT);
 	while (status & INT_EN_MASK && host->req_in_progress) {
 		omap_hsmmc_do_irq(host, status);
 
 		/* Flush posted write */
-		status = OMAP_HSMMC_READ(host->base, STAT);
+		status = OMAP_HSMMC_READ(host, STAT);
 	}
 
 	return IRQ_HANDLED;
@@ -1131,10 +1131,10 @@ static void set_sd_bus_power(struct omap_hsmmc_host *host)
 {
 	unsigned long i;
 
-	OMAP_HSMMC_WRITE(host->base, HCTL,
-			 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
+	OMAP_HSMMC_WRITE(host, HCTL,
+			 OMAP_HSMMC_READ(host, HCTL) | SDBP);
 	for (i = 0; i < loops_per_jiffy; i++) {
-		if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
+		if (OMAP_HSMMC_READ(host, HCTL) & SDBP)
 			break;
 		cpu_relax();
 	}
@@ -1171,9 +1171,9 @@ static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
 	if (ret != 0)
 		goto err;
 
-	OMAP_HSMMC_WRITE(host->base, HCTL,
-		OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
-	reg_val = OMAP_HSMMC_READ(host->base, HCTL);
+	OMAP_HSMMC_WRITE(host, HCTL,
+		OMAP_HSMMC_READ(host, HCTL) & SDVSCLR);
+	reg_val = OMAP_HSMMC_READ(host, HCTL);
 
 	/*
 	 * If a MMC dual voltage card is detected, the set_ios fn calls
@@ -1195,7 +1195,7 @@ static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
 	else
 		reg_val |= SDVS30;
 
-	OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
+	OMAP_HSMMC_WRITE(host, HCTL, reg_val);
 	set_sd_bus_power(host);
 
 	return 0;
@@ -1396,7 +1396,7 @@ static void set_data_timeout(struct omap_hsmmc_host *host,
 	unsigned int timeout, cycle_ns;
 	uint32_t reg, clkd, dto = 0;
 
-	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
+	reg = OMAP_HSMMC_READ(host, SYSCTL);
 	clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 	if (clkd == 0)
 		clkd = 1;
@@ -1423,7 +1423,7 @@ static void set_data_timeout(struct omap_hsmmc_host *host,
 
 	reg &= ~DTO_MASK;
 	reg |= dto << DTO_SHIFT;
-	OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
+	OMAP_HSMMC_WRITE(host, SYSCTL, reg);
 }
 
 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
@@ -1433,7 +1433,7 @@ static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
 
 	if (!req->data)
 		return;
-	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
+	OMAP_HSMMC_WRITE(host, BLK, (req->data->blksz)
 				| (req->data->blocks << 16));
 	set_data_timeout(host, req->data->timeout_ns,
 				req->data->timeout_clks);
@@ -1451,7 +1451,7 @@ omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
 	host->data = req->data;
 
 	if (req->data == NULL) {
-		OMAP_HSMMC_WRITE(host->base, BLK, 0);
+		OMAP_HSMMC_WRITE(host, BLK, 0);
 		/*
 		 * Set an arbitrary 100ms data timeout for commands with
 		 * busy signal.
@@ -1588,7 +1588,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		/* Only MMC1 can interface at 3V without some flavor
 		 * of external transceiver; but they all handle 1.8V.
 		 */
-		if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
+		if ((OMAP_HSMMC_READ(host, HCTL) & SDVSDET) &&
 			(ios->vdd == DUAL_VOLT_OCR_BIT)) {
 				/*
 				 * The mmc_select_voltage fn of the core does
@@ -1651,11 +1651,11 @@ static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
 		capa = VS18;
 	}
 
-	value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
-	OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
+	value = OMAP_HSMMC_READ(host, HCTL) & ~SDVS_MASK;
+	OMAP_HSMMC_WRITE(host, HCTL, value | hctl);
 
-	value = OMAP_HSMMC_READ(host->base, CAPA);
-	OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
+	value = OMAP_HSMMC_READ(host, CAPA);
+	OMAP_HSMMC_WRITE(host, CAPA, value | capa);
 
 	/* Set SD bus power bit */
 	set_sd_bus_power(host);
@@ -1706,17 +1706,17 @@ static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
 	pm_runtime_get_sync(host->dev);
 
 	seq_printf(s, "CON:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host->base, CON));
+			OMAP_HSMMC_READ(host, CON));
 	seq_printf(s, "HCTL:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host->base, HCTL));
+			OMAP_HSMMC_READ(host, HCTL));
 	seq_printf(s, "SYSCTL:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host->base, SYSCTL));
+			OMAP_HSMMC_READ(host, SYSCTL));
 	seq_printf(s, "IE:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host->base, IE));
+			OMAP_HSMMC_READ(host, IE));
 	seq_printf(s, "ISE:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host->base, ISE));
+			OMAP_HSMMC_READ(host, ISE));
 	seq_printf(s, "CAPA:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host->base, CAPA));
+			OMAP_HSMMC_READ(host, CAPA));
 
 	pm_runtime_mark_last_busy(host->dev);
 	pm_runtime_put_autosuspend(host->dev);
@@ -2192,8 +2192,8 @@ static int omap_hsmmc_suspend(struct device *dev)
 
 	if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
 		omap_hsmmc_disable_irq(host);
-		OMAP_HSMMC_WRITE(host->base, HCTL,
-				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
+		OMAP_HSMMC_WRITE(host, HCTL,
+				OMAP_HSMMC_READ(host, HCTL) & ~SDBP);
 	}
 
 	if (host->dbclk)
-- 
1.9.1.286.g5172cb3

[PATCH 2/5] mmc: host: omap_hsmmc: add reg_offset field

[Felipe Balbi]

by saving reg_offset inside our host structure
we can ioremap the correct area, make use of
resource_size() and make sure newer versions
of the IP have access to the new set of registers
which were added back in OMAP4.

Signed-off-by: Felipe Balbi <balbi@ti.com>
---
 drivers/mmc/host/omap_hsmmc.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index a8f1e08..d46f768 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -152,10 +152,10 @@
  * MMC Host controller read/write API's
  */
 #define OMAP_HSMMC_READ(host, reg)	\
-	__raw_readl((host)->base + OMAP_HSMMC_##reg)
+	__raw_readl((host)->base + OMAP_HSMMC_##reg + host->reg_offset)
 
 #define OMAP_HSMMC_WRITE(host, reg, val) \
-	__raw_writel((val), (host)->base + OMAP_HSMMC_##reg)
+	__raw_writel((val), (host)->base + OMAP_HSMMC_##reg + host->reg_offset)
 
 struct omap_hsmmc_next {
 	unsigned int	dma_len;
@@ -184,6 +184,7 @@ struct omap_hsmmc_host {
 	void	__iomem		*base;
 	resource_size_t		mapbase;
 	spinlock_t		irq_lock; /* Prevent races with irq handler */
+	unsigned int		reg_offset;
 	unsigned int		dma_len;
 	unsigned int		dma_sg_idx;
 	unsigned char		bus_mode;
@@ -1354,8 +1355,8 @@ static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
 
 	chan = omap_hsmmc_get_dma_chan(host, data);
 
-	cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
-	cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
+	cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA + host->reg_offset;
+	cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA + host->reg_offset;
 	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	cfg.src_maxburst = data->blksz / 4;
@@ -1903,8 +1904,9 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 	host->dma_ch	= -1;
 	host->irq	= irq;
 	host->slot_id	= 0;
-	host->mapbase	= res->start + pdata->reg_offset;
-	host->base	= ioremap(host->mapbase, SZ_4K);
+	host->reg_offset = pdata->reg_offset;
+	host->mapbase	= res->start;
+	host->base	= ioremap(res->start, resource_size(res));
 	host->power_mode = MMC_POWER_OFF;
 	host->next_data.cookie = 1;
 	host->pbias_enabled = 0;
-- 
1.9.1.286.g5172cb3

[PATCH 3/5] mmc: host: omap_hsmmc: introduce new accessor functions

[Felipe Balbi]

we introduce new accessors which provide for register
access with and without offsets.

This is just to make sure newer versions of the IP
can access the new registers prepended at the beginning
of the address space.

Signed-off-by: Felipe Balbi <balbi@ti.com>
---
 drivers/mmc/host/omap_hsmmc.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index d46f768..e596c6a 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -211,6 +211,42 @@ struct omap_hsmmc_host {
 	struct	omap_mmc_platform_data	*pdata;
 };
 
+static inline int _omap_hsmmc_read(struct omap_hsmmc_host *host,
+		u32 reg, bool offset)
+{
+	return readl(host->base + reg + (offset ? host->reg_offset : 0));
+}
+
+static inline void _omap_hsmmc_write(struct omap_hsmmc_host *host,
+		u32 reg, u32 val, bool offset)
+{
+	writel(val, host->base + reg + (offset ? host->reg_offset : 0));
+}
+
+static inline int omap_hsmmc_read_offset(struct omap_hsmmc_host *host,
+		u32 reg)
+{
+	return _omap_hsmmc_read(host, reg, true);
+}
+
+static inline void omap_hsmmc_write_offset(struct omap_hsmmc_host *host,
+		u32 reg, u32 val)
+{
+	_omap_hsmmc_write(host, reg, val, true);
+}
+
+static inline int omap_hsmmc_read_no_offset(struct omap_hsmmc_host *host,
+		u32 reg)
+{
+	return _omap_hsmmc_read(host, reg, false);
+}
+
+static inline void omap_hsmmc_write_no_offset(struct omap_hsmmc_host *host,
+		u32 reg, u32 val)
+{
+	_omap_hsmmc_write(host, reg, val, false);
+}
+
 struct omap_mmc_of_data {
 	u32 reg_offset;
 	u8 controller_flags;
-- 
1.9.1.286.g5172cb3

Re: [PATCH 3/5] mmc: host: omap_hsmmc: introduce new accessor functions

[Balaji T K]

On Thursday 27 March 2014 05:34 AM, Felipe Balbi wrote:
> we introduce new accessors which provide for register
> access with and without offsets.
>
> This is just to make sure newer versions of the IP
> can access the new registers prepended at the beginning
> of the address space.
>
> Signed-off-by: Felipe Balbi <balbi@ti.com>
> ---
>   drivers/mmc/host/omap_hsmmc.c | 36 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 36 insertions(+)
>
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index d46f768..e596c6a 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -211,6 +211,42 @@ struct omap_hsmmc_host {
>   	struct	omap_mmc_platform_data	*pdata;
>   };
>
> +static inline int _omap_hsmmc_read(struct omap_hsmmc_host *host,
> +		u32 reg, bool offset)
> +{
> +	return readl(host->base + reg + (offset ? host->reg_offset : 0));
> +}
> +
> +static inline void _omap_hsmmc_write(struct omap_hsmmc_host *host,
> +		u32 reg, u32 val, bool offset)
> +{
> +	writel(val, host->base + reg + (offset ? host->reg_offset : 0));
> +}
> +
> +static inline int omap_hsmmc_read_offset(struct omap_hsmmc_host *host,

I think you can rename this function as just omap_hsmmc_read
(removing _offset suffix)

> +		u32 reg)
> +{
> +	return _omap_hsmmc_read(host, reg, true);
> +}
> +
> +static inline void omap_hsmmc_write_offset(struct omap_hsmmc_host *host,

and this one as omap_hsmmc_write since this version of read/write is most often
used, the one with no_offset might be used less often.

[PATCH 4/5] mmc: host: omap_hsmmc: switch over to new accessors

[Felipe Balbi]

the newly introduced accessor funtions will help
dealing with register access which shouldn't be
done with offset in consideration.

Signed-off-by: Felipe Balbi <balbi@ti.com>
---
 drivers/mmc/host/omap_hsmmc.c | 200 ++++++++++++++++++++----------------------
 1 file changed, 96 insertions(+), 104 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index e596c6a..d32f6ac 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -148,15 +148,6 @@
  */
 #define mmc_slot(host)		(host->pdata->slots[host->slot_id])
 
-/*
- * MMC Host controller read/write API's
- */
-#define OMAP_HSMMC_READ(host, reg)	\
-	__raw_readl((host)->base + OMAP_HSMMC_##reg + host->reg_offset)
-
-#define OMAP_HSMMC_WRITE(host, reg, val) \
-	__raw_writel((val), (host)->base + OMAP_HSMMC_##reg + host->reg_offset)
-
 struct omap_hsmmc_next {
 	unsigned int	dma_len;
 	s32		cookie;
@@ -529,8 +520,8 @@ static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
  */
 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 {
-	OMAP_HSMMC_WRITE(host, SYSCTL,
-		OMAP_HSMMC_READ(host, SYSCTL) | CEN);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_SYSCTL,
+		omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) | CEN);
 }
 
 /*
@@ -538,9 +529,9 @@ static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
  */
 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 {
-	OMAP_HSMMC_WRITE(host, SYSCTL,
-		OMAP_HSMMC_READ(host, SYSCTL) & ~CEN);
-	if ((OMAP_HSMMC_READ(host, SYSCTL) & CEN) != 0x0)
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_SYSCTL,
+		omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) & ~CEN);
+	if ((omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) & CEN) != 0x0)
 		dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 }
 
@@ -558,16 +549,16 @@ static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 	if (cmd->opcode == MMC_ERASE)
 		irq_mask &= ~DTO_EN;
 
-	OMAP_HSMMC_WRITE(host, STAT, STAT_CLEAR);
-	OMAP_HSMMC_WRITE(host, ISE, irq_mask);
-	OMAP_HSMMC_WRITE(host, IE, irq_mask);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_STAT, STAT_CLEAR);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_ISE, irq_mask);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_IE, irq_mask);
 }
 
 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 {
-	OMAP_HSMMC_WRITE(host, ISE, 0);
-	OMAP_HSMMC_WRITE(host, IE, 0);
-	OMAP_HSMMC_WRITE(host, STAT, STAT_CLEAR);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_ISE, 0);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_IE, 0);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_STAT, STAT_CLEAR);
 }
 
 /* Calculate divisor for the given clock frequency */
@@ -595,17 +586,17 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 
 	omap_hsmmc_stop_clock(host);
 
-	regval = OMAP_HSMMC_READ(host, SYSCTL);
+	regval = omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL);
 	regval = regval & ~(CLKD_MASK | DTO_MASK);
 	clkdiv = calc_divisor(host, ios);
 	regval = regval | (clkdiv << 6) | (DTO << 16);
-	OMAP_HSMMC_WRITE(host, SYSCTL, regval);
-	OMAP_HSMMC_WRITE(host, SYSCTL,
-		OMAP_HSMMC_READ(host, SYSCTL) | ICE);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_SYSCTL, regval);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_SYSCTL,
+		omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) | ICE);
 
 	/* Wait till the ICS bit is set */
 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
-	while ((OMAP_HSMMC_READ(host, SYSCTL) & ICS) != ICS
+	while ((omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) & ICS) != ICS
 		&& time_before(jiffies, timeout))
 		cpu_relax();
 
@@ -620,14 +611,14 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 	 */
 	if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
 	    (ios->timing != MMC_TIMING_UHS_DDR50) &&
-	    ((OMAP_HSMMC_READ(host, CAPA) & HSS) == HSS)) {
-		regval = OMAP_HSMMC_READ(host, HCTL);
+	    ((omap_hsmmc_read_offset(host, OMAP_HSMMC_CAPA) & HSS) == HSS)) {
+		regval = omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL);
 		if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 			regval |= HSPE;
 		else
 			regval &= ~HSPE;
 
-		OMAP_HSMMC_WRITE(host, HCTL, regval);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL, regval);
 	}
 
 	omap_hsmmc_start_clock(host);
@@ -638,24 +629,24 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 	struct mmc_ios *ios = &host->mmc->ios;
 	u32 con;
 
-	con = OMAP_HSMMC_READ(host, CON);
+	con = omap_hsmmc_read_offset(host, OMAP_HSMMC_CON);
 	if (ios->timing == MMC_TIMING_UHS_DDR50)
 		con |= DDR;	/* configure in DDR mode */
 	else
 		con &= ~DDR;
 	switch (ios->bus_width) {
 	case MMC_BUS_WIDTH_8:
-		OMAP_HSMMC_WRITE(host, CON, con | DW8);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_CON, con | DW8);
 		break;
 	case MMC_BUS_WIDTH_4:
-		OMAP_HSMMC_WRITE(host, CON, con & ~DW8);
-		OMAP_HSMMC_WRITE(host, HCTL,
-			OMAP_HSMMC_READ(host, HCTL) | FOUR_BIT);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_CON, con & ~DW8);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL,
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) | FOUR_BIT);
 		break;
 	case MMC_BUS_WIDTH_1:
-		OMAP_HSMMC_WRITE(host, CON, con & ~DW8);
-		OMAP_HSMMC_WRITE(host, HCTL,
-			OMAP_HSMMC_READ(host, HCTL) & ~FOUR_BIT);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_CON, con & ~DW8);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL,
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) & ~FOUR_BIT);
 		break;
 	}
 }
@@ -665,11 +656,11 @@ static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 	struct mmc_ios *ios = &host->mmc->ios;
 	u32 con;
 
-	con = OMAP_HSMMC_READ(host, CON);
+	con = omap_hsmmc_read_offset(host, OMAP_HSMMC_CON);
 	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
-		OMAP_HSMMC_WRITE(host, CON, con | OD);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_CON, con | OD);
 	else
-		OMAP_HSMMC_WRITE(host, CON, con & ~OD);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_CON, con & ~OD);
 }
 
 #ifdef CONFIG_PM
@@ -684,10 +675,10 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 	u32 hctl, capa;
 	unsigned long timeout;
 
-	if (host->con == OMAP_HSMMC_READ(host, CON) &&
-	    host->hctl == OMAP_HSMMC_READ(host, HCTL) &&
-	    host->sysctl == OMAP_HSMMC_READ(host, SYSCTL) &&
-	    host->capa == OMAP_HSMMC_READ(host, CAPA))
+	if (host->con == omap_hsmmc_read_offset(host, OMAP_HSMMC_CON) &&
+	    host->hctl == omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) &&
+	    host->sysctl == omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) &&
+	    host->capa == omap_hsmmc_read_offset(host, OMAP_HSMMC_CAPA))
 		return 0;
 
 	host->context_loss++;
@@ -704,17 +695,17 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 		capa = VS18;
 	}
 
-	OMAP_HSMMC_WRITE(host, HCTL,
-			OMAP_HSMMC_READ(host, HCTL) | hctl);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL,
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) | hctl);
 
-	OMAP_HSMMC_WRITE(host, CAPA,
-			OMAP_HSMMC_READ(host, CAPA) | capa);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_CAPA,
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_CAPA) | capa);
 
-	OMAP_HSMMC_WRITE(host, HCTL,
-			OMAP_HSMMC_READ(host, HCTL) | SDBP);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL,
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) | SDBP);
 
 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
-	while ((OMAP_HSMMC_READ(host, HCTL) & SDBP) != SDBP
+	while ((omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) & SDBP) != SDBP
 		&& time_before(jiffies, timeout))
 		;
 
@@ -741,10 +732,10 @@ out:
  */
 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 {
-	host->con =  OMAP_HSMMC_READ(host, CON);
-	host->hctl = OMAP_HSMMC_READ(host, HCTL);
-	host->sysctl =  OMAP_HSMMC_READ(host, SYSCTL);
-	host->capa = OMAP_HSMMC_READ(host, CAPA);
+	host->con =  omap_hsmmc_read_offset(host, OMAP_HSMMC_CON);
+	host->hctl = omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL);
+	host->sysctl =  omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL);
+	host->capa = omap_hsmmc_read_offset(host, OMAP_HSMMC_CAPA);
 }
 
 #else
@@ -774,20 +765,20 @@ static void send_init_stream(struct omap_hsmmc_host *host)
 
 	disable_irq(host->irq);
 
-	OMAP_HSMMC_WRITE(host, IE, INT_EN_MASK);
-	OMAP_HSMMC_WRITE(host, CON,
-		OMAP_HSMMC_READ(host, CON) | INIT_STREAM);
-	OMAP_HSMMC_WRITE(host, CMD, INIT_STREAM_CMD);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_IE, INT_EN_MASK);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_CON,
+		omap_hsmmc_read_offset(host, OMAP_HSMMC_CON) | INIT_STREAM);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_CMD, INIT_STREAM_CMD);
 
 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 	while ((reg != CC_EN) && time_before(jiffies, timeout))
-		reg = OMAP_HSMMC_READ(host, STAT) & CC_EN;
+		reg = omap_hsmmc_read_offset(host, OMAP_HSMMC_STAT) & CC_EN;
 
-	OMAP_HSMMC_WRITE(host, CON,
-		OMAP_HSMMC_READ(host, CON) & ~INIT_STREAM);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_CON,
+		omap_hsmmc_read_offset(host, OMAP_HSMMC_CON) & ~INIT_STREAM);
 
-	OMAP_HSMMC_WRITE(host, STAT, STAT_CLEAR);
-	OMAP_HSMMC_READ(host, STAT);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_STAT, STAT_CLEAR);
+	omap_hsmmc_read_offset(host, OMAP_HSMMC_STAT);
 
 	enable_irq(host->irq);
 }
@@ -866,7 +857,7 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 	if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
 	    host->mrq->sbc) {
 		cmdreg |= ACEN_ACMD23;
-		OMAP_HSMMC_WRITE(host, SDMASA, host->mrq->sbc->arg);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_SDMASA, host->mrq->sbc->arg);
 	}
 	if (data) {
 		cmdreg |= DP_SELECT | MSBS | BCE;
@@ -881,8 +872,8 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 
 	host->req_in_progress = 1;
 
-	OMAP_HSMMC_WRITE(host, ARG, cmd->arg);
-	OMAP_HSMMC_WRITE(host, CMD, cmdreg);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_ARG, cmd->arg);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_CMD, cmdreg);
 }
 
 static int
@@ -970,13 +961,13 @@ omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 	if (cmd->flags & MMC_RSP_PRESENT) {
 		if (cmd->flags & MMC_RSP_136) {
 			/* response type 2 */
-			cmd->resp[3] = OMAP_HSMMC_READ(host, RSP10);
-			cmd->resp[2] = OMAP_HSMMC_READ(host, RSP32);
-			cmd->resp[1] = OMAP_HSMMC_READ(host, RSP54);
-			cmd->resp[0] = OMAP_HSMMC_READ(host, RSP76);
+			cmd->resp[3] = omap_hsmmc_read_offset(host, OMAP_HSMMC_RSP10);
+			cmd->resp[2] = omap_hsmmc_read_offset(host, OMAP_HSMMC_RSP32);
+			cmd->resp[1] = omap_hsmmc_read_offset(host, OMAP_HSMMC_RSP54);
+			cmd->resp[0] = omap_hsmmc_read_offset(host, OMAP_HSMMC_RSP76);
 		} else {
 			/* response types 1, 1b, 3, 4, 5, 6 */
-			cmd->resp[0] = OMAP_HSMMC_READ(host, RSP10);
+			cmd->resp[0] = omap_hsmmc_read_offset(host, OMAP_HSMMC_RSP10);
 		}
 	}
 	if ((host->data == NULL && !host->response_busy) || cmd->error)
@@ -1059,25 +1050,25 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 	unsigned long i = 0;
 	unsigned long limit = MMC_TIMEOUT_US;
 
-	OMAP_HSMMC_WRITE(host, SYSCTL,
-			 OMAP_HSMMC_READ(host, SYSCTL) | bit);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_SYSCTL,
+			 omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) | bit);
 
 	/*
 	 * OMAP4 ES2 and greater has an updated reset logic.
 	 * Monitor a 0->1 transition first
 	 */
 	if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
-		while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit))
+		while ((!(omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) & bit))
 					&& (i++ < limit))
 			udelay(1);
 	}
 	i = 0;
 
-	while ((OMAP_HSMMC_READ(host, SYSCTL) & bit) &&
+	while ((omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) & bit) &&
 		(i++ < limit))
 		udelay(1);
 
-	if (OMAP_HSMMC_READ(host, SYSCTL) & bit)
+	if (omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL) & bit)
 		dev_err(mmc_dev(host->mmc),
 			"Timeout waiting on controller reset in %s\n",
 			__func__);
@@ -1120,7 +1111,7 @@ static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 
 		if (status & ACE_EN) {
 			u32 ac12;
-			ac12 = OMAP_HSMMC_READ(host, AC12);
+			ac12 = omap_hsmmc_read_offset(host, OMAP_HSMMC_AC12);
 			if (!(ac12 & ACNE) && host->mrq->sbc) {
 				end_cmd = 1;
 				if (ac12 & ACTO)
@@ -1138,7 +1129,7 @@ static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 		}
 	}
 
-	OMAP_HSMMC_WRITE(host, STAT, status);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_STAT, status);
 	if (end_cmd || ((status & CC_EN) && host->cmd))
 		omap_hsmmc_cmd_done(host, host->cmd);
 	if ((end_trans || (status & TC_EN)) && host->mrq)
@@ -1153,12 +1144,12 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
 	struct omap_hsmmc_host *host = dev_id;
 	int status;
 
-	status = OMAP_HSMMC_READ(host, STAT);
+	status = omap_hsmmc_read_offset(host, OMAP_HSMMC_STAT);
 	while (status & INT_EN_MASK && host->req_in_progress) {
 		omap_hsmmc_do_irq(host, status);
 
 		/* Flush posted write */
-		status = OMAP_HSMMC_READ(host, STAT);
+		status = omap_hsmmc_read_offset(host, OMAP_HSMMC_STAT);
 	}
 
 	return IRQ_HANDLED;
@@ -1168,10 +1159,10 @@ static void set_sd_bus_power(struct omap_hsmmc_host *host)
 {
 	unsigned long i;
 
-	OMAP_HSMMC_WRITE(host, HCTL,
-			 OMAP_HSMMC_READ(host, HCTL) | SDBP);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL,
+			 omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) | SDBP);
 	for (i = 0; i < loops_per_jiffy; i++) {
-		if (OMAP_HSMMC_READ(host, HCTL) & SDBP)
+		if (omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) & SDBP)
 			break;
 		cpu_relax();
 	}
@@ -1208,9 +1199,9 @@ static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
 	if (ret != 0)
 		goto err;
 
-	OMAP_HSMMC_WRITE(host, HCTL,
-		OMAP_HSMMC_READ(host, HCTL) & SDVSCLR);
-	reg_val = OMAP_HSMMC_READ(host, HCTL);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL,
+		omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) & SDVSCLR);
+	reg_val = omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL);
 
 	/*
 	 * If a MMC dual voltage card is detected, the set_ios fn calls
@@ -1232,7 +1223,7 @@ static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
 	else
 		reg_val |= SDVS30;
 
-	OMAP_HSMMC_WRITE(host, HCTL, reg_val);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL, reg_val);
 	set_sd_bus_power(host);
 
 	return 0;
@@ -1433,7 +1424,7 @@ static void set_data_timeout(struct omap_hsmmc_host *host,
 	unsigned int timeout, cycle_ns;
 	uint32_t reg, clkd, dto = 0;
 
-	reg = OMAP_HSMMC_READ(host, SYSCTL);
+	reg = omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL);
 	clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 	if (clkd == 0)
 		clkd = 1;
@@ -1460,7 +1451,7 @@ static void set_data_timeout(struct omap_hsmmc_host *host,
 
 	reg &= ~DTO_MASK;
 	reg |= dto << DTO_SHIFT;
-	OMAP_HSMMC_WRITE(host, SYSCTL, reg);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_SYSCTL, reg);
 }
 
 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
@@ -1470,7 +1461,7 @@ static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
 
 	if (!req->data)
 		return;
-	OMAP_HSMMC_WRITE(host, BLK, (req->data->blksz)
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_BLK, (req->data->blksz)
 				| (req->data->blocks << 16));
 	set_data_timeout(host, req->data->timeout_ns,
 				req->data->timeout_clks);
@@ -1488,7 +1479,7 @@ omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
 	host->data = req->data;
 
 	if (req->data == NULL) {
-		OMAP_HSMMC_WRITE(host, BLK, 0);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_BLK, 0);
 		/*
 		 * Set an arbitrary 100ms data timeout for commands with
 		 * busy signal.
@@ -1625,7 +1616,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		/* Only MMC1 can interface at 3V without some flavor
 		 * of external transceiver; but they all handle 1.8V.
 		 */
-		if ((OMAP_HSMMC_READ(host, HCTL) & SDVSDET) &&
+		if ((omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) & SDVSDET) &&
 			(ios->vdd == DUAL_VOLT_OCR_BIT)) {
 				/*
 				 * The mmc_select_voltage fn of the core does
@@ -1688,11 +1679,11 @@ static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
 		capa = VS18;
 	}
 
-	value = OMAP_HSMMC_READ(host, HCTL) & ~SDVS_MASK;
-	OMAP_HSMMC_WRITE(host, HCTL, value | hctl);
+	value = omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL) & ~SDVS_MASK;
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL, value | hctl);
 
-	value = OMAP_HSMMC_READ(host, CAPA);
-	OMAP_HSMMC_WRITE(host, CAPA, value | capa);
+	value = omap_hsmmc_read_offset(host, OMAP_HSMMC_CAPA);
+	omap_hsmmc_write_offset(host, OMAP_HSMMC_CAPA, value | capa);
 
 	/* Set SD bus power bit */
 	set_sd_bus_power(host);
@@ -1743,17 +1734,17 @@ static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
 	pm_runtime_get_sync(host->dev);
 
 	seq_printf(s, "CON:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host, CON));
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_CON));
 	seq_printf(s, "HCTL:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host, HCTL));
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL));
 	seq_printf(s, "SYSCTL:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host, SYSCTL));
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_SYSCTL));
 	seq_printf(s, "IE:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host, IE));
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_IE));
 	seq_printf(s, "ISE:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host, ISE));
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_ISE));
 	seq_printf(s, "CAPA:\t\t0x%08x\n",
-			OMAP_HSMMC_READ(host, CAPA));
+			omap_hsmmc_read_offset(host, OMAP_HSMMC_CAPA));
 
 	pm_runtime_mark_last_busy(host->dev);
 	pm_runtime_put_autosuspend(host->dev);
@@ -2230,8 +2221,9 @@ static int omap_hsmmc_suspend(struct device *dev)
 
 	if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
 		omap_hsmmc_disable_irq(host);
-		OMAP_HSMMC_WRITE(host, HCTL,
-				OMAP_HSMMC_READ(host, HCTL) & ~SDBP);
+		omap_hsmmc_write_offset(host, OMAP_HSMMC_HCTL,
+				omap_hsmmc_read_offset(host, OMAP_HSMMC_HCTL)
+				& ~SDBP);
 	}
 
 	if (host->dbclk)
-- 
1.9.1.286.g5172cb3

[PATCH 5/5] mmc: host: omap_hsmmc: set max_blk_size correctly

[Felipe Balbi]

now that we can finally read the new registers for
new versions of the mmc IP, we can set max_blk_size
correctly depending on the version of the IP we're
running on.

Signed-off-by: Felipe Balbi <balbi@ti.com>
---
 drivers/mmc/host/omap_hsmmc.c | 45 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index d32f6ac..ae5583e 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -62,6 +62,18 @@
 #define OMAP_HSMMC_AC12		0x013C
 #define OMAP_HSMMC_CAPA		0x0140
 
+/* OMAP HSMMC Host Controller Register (NEW)
+ *
+ * NOTE: DO NOT READ THESE WITH OFFSET
+ */
+#define OMAP_HSMMC_HL_REV	0x0000
+#define OMAP_HSMMC_HL_HWINFO	0x0004
+#	define OMAP_HSMMC_HL_HWINFO_MADMA_EN	(1 << 0)
+#	define OMAP_HSMMC_HL_HWINFO_MERGE_MEM	(1 << 1)
+#	define OMAP_HSMMC_HL_HWINFO_MEM_SIZE(x)	(((x) & (0x0f << 2)) >> 2)
+#	define OMAP_HSMMC_HL_HWINFO_RETMODE	(1 << 6)
+#define OMAP_HSMMC_HL_SYSCONFIG	0x0010
+
 #define VS18			(1 << 26)
 #define VS30			(1 << 25)
 #define HSS			(1 << 21)
@@ -1867,6 +1879,37 @@ static inline struct omap_mmc_platform_data
 }
 #endif
 
+static void omap_hsmmc_set_max_blk_size(struct omap_hsmmc_host *host)
+{
+	struct mmc_host *mmc = host->mmc;
+
+	if (of_device_is_compatible(host->dev->of_node, "ti,omap4-hsmmc")) {
+		u32 mem;
+		u32 reg;
+
+		reg = omap_hsmmc_read_no_offset(host, OMAP_HSMMC_HL_HWINFO);
+		mem = OMAP_HSMMC_HL_HWINFO_MEM_SIZE(reg);
+
+		switch (mem) {
+		case 1:
+			mmc->max_blk_size = 512;
+			break;
+		case 2:
+			mmc->max_blk_size = 1024;
+			break;
+		case 4:
+			/* FALLTHROUGH */
+		case 8:
+			/* FALLTHROUGH */
+		default:
+			mmc->max_blk_size = 2048;
+			break;
+		}
+	} else {
+		mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
+	}
+}
+
 static int omap_hsmmc_probe(struct platform_device *pdev)
 {
 	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
@@ -1986,7 +2029,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 	 * as we want. */
 	mmc->max_segs = 1024;
 
-	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
+	omap_hsmmc_set_max_blk_size(host);
 	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 	mmc->max_seg_size = mmc->max_req_size;
-- 
1.9.1.286.g5172cb3

Re: [PATCH 5/5] mmc: host: omap_hsmmc: set max_blk_size correctly

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1072 bytes --]

Hi,

On Wed, Mar 26, 2014 at 07:04:50PM -0500, Felipe Balbi wrote:
> @@ -1867,6 +1879,37 @@ static inline struct omap_mmc_platform_data
>  }
>  #endif
>  
> +static void omap_hsmmc_set_max_blk_size(struct omap_hsmmc_host *host)
> +{
> +	struct mmc_host *mmc = host->mmc;
> +
> +	if (of_device_is_compatible(host->dev->of_node, "ti,omap4-hsmmc")) {
> +		u32 mem;
> +		u32 reg;
> +
> +		reg = omap_hsmmc_read_no_offset(host, OMAP_HSMMC_HL_HWINFO);
> +		mem = OMAP_HSMMC_HL_HWINFO_MEM_SIZE(reg);
> +
> +		switch (mem) {
> +		case 1:
> +			mmc->max_blk_size = 512;
> +			break;
> +		case 2:
> +			mmc->max_blk_size = 1024;
> +			break;
> +		case 4:
> +			/* FALLTHROUGH */
> +		case 8:
> +			/* FALLTHROUGH */
> +		default:
> +			mmc->max_blk_size = 2048;
> +			break;
> +		}
> +	} else {
> +		mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */

looks like here, we could read CAPA register to figure out if older
devices support bigger block sizes. According to TRM, omap3 should
support 1024 just fine.

-- 
balbi

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Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 792 bytes --]

Hi,

On Wed, Mar 26, 2014 at 07:04:45PM -0500, Felipe Balbi wrote:
> this series lets us access the newer registers introduced
> back in OMAP4 which give us some valid information about
> the OMAP HSMMC IP like max block size, support for ADMA,
> support for Retention.
> 
> Right now, only setting max_blk_size correctly as supporting
> ADMA and Retention will take a lot of work.
> 
> Tested on OMAP5 uEVM.
> 
> Felipe Balbi (5):
>   mmc: host: omap_hsmmc: pass host as an argument
>   mmc: host: omap_hsmmc: add reg_offset field
>   mmc: host: omap_hsmmc: introduce new accessor functions
>   mmc: host: omap_hsmmc: switch over to new accessors
>   mmc: host: omap_hsmmc: set max_blk_size correctly

this has been here for almost a month, any comments ?

-- 
balbi

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Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Balaji T K]

On Monday 21 April 2014 11:02 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, Mar 26, 2014 at 07:04:45PM -0500, Felipe Balbi wrote:
>> this series lets us access the newer registers introduced
>> back in OMAP4 which give us some valid information about
>> the OMAP HSMMC IP like max block size, support for ADMA,
>> support for Retention.
>>
>> Right now, only setting max_blk_size correctly as supporting
>> ADMA and Retention will take a lot of work.
>>
>> Tested on OMAP5 uEVM.
>>
>> Felipe Balbi (5):
>>    mmc: host: omap_hsmmc: pass host as an argument
>>    mmc: host: omap_hsmmc: add reg_offset field
>>    mmc: host: omap_hsmmc: introduce new accessor functions
>>    mmc: host: omap_hsmmc: switch over to new accessors
>>    mmc: host: omap_hsmmc: set max_blk_size correctly

Got mislead by your reply to this series, about the alternative way of
reading memory size from CAPA register

>
> this has been here for almost a month, any comments ?
>

Do you see any performance impact with this series ?

Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1319 bytes --]

Hi,

On Tue, Apr 22, 2014 at 09:00:12PM +0530, Balaji T K wrote:
> On Monday 21 April 2014 11:02 PM, Felipe Balbi wrote:
> >Hi,
> >
> >On Wed, Mar 26, 2014 at 07:04:45PM -0500, Felipe Balbi wrote:
> >>this series lets us access the newer registers introduced
> >>back in OMAP4 which give us some valid information about
> >>the OMAP HSMMC IP like max block size, support for ADMA,
> >>support for Retention.
> >>
> >>Right now, only setting max_blk_size correctly as supporting
> >>ADMA and Retention will take a lot of work.
> >>
> >>Tested on OMAP5 uEVM.
> >>
> >>Felipe Balbi (5):
> >>   mmc: host: omap_hsmmc: pass host as an argument
> >>   mmc: host: omap_hsmmc: add reg_offset field
> >>   mmc: host: omap_hsmmc: introduce new accessor functions
> >>   mmc: host: omap_hsmmc: switch over to new accessors
> >>   mmc: host: omap_hsmmc: set max_blk_size correctly
> 
> Got mislead by your reply to this series, about the alternative way of
> reading memory size from CAPA register

sure, we can do that if you prefer, I just felt I wouldn't touch
platforms I can't really test :-s

> >this has been here for almost a month, any comments ?
> >
> 
> Do you see any performance impact with this series ?

in the normal case ? no... it helps only with large transfers

-- 
balbi

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Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1345 bytes --]

On Tue, Apr 22, 2014 at 10:48:58AM -0500, Felipe Balbi wrote:
> Hi,
> 
> On Tue, Apr 22, 2014 at 09:00:12PM +0530, Balaji T K wrote:
> > On Monday 21 April 2014 11:02 PM, Felipe Balbi wrote:
> > >Hi,
> > >
> > >On Wed, Mar 26, 2014 at 07:04:45PM -0500, Felipe Balbi wrote:
> > >>this series lets us access the newer registers introduced
> > >>back in OMAP4 which give us some valid information about
> > >>the OMAP HSMMC IP like max block size, support for ADMA,
> > >>support for Retention.
> > >>
> > >>Right now, only setting max_blk_size correctly as supporting
> > >>ADMA and Retention will take a lot of work.
> > >>
> > >>Tested on OMAP5 uEVM.
> > >>
> > >>Felipe Balbi (5):
> > >>   mmc: host: omap_hsmmc: pass host as an argument
> > >>   mmc: host: omap_hsmmc: add reg_offset field
> > >>   mmc: host: omap_hsmmc: introduce new accessor functions
> > >>   mmc: host: omap_hsmmc: switch over to new accessors
> > >>   mmc: host: omap_hsmmc: set max_blk_size correctly
> > 
> > Got mislead by your reply to this series, about the alternative way of
> > reading memory size from CAPA register
> 
> sure, we can do that if you prefer, I just felt I wouldn't touch
> platforms I can't really test :-s

any comments ? do you prefer to change max_blk_size to read CAPA for the
other platforms ?

-- 
balbi

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Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Balaji T K]

On Tuesday 22 April 2014 09:18 PM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Apr 22, 2014 at 09:00:12PM +0530, Balaji T K wrote:
>> On Monday 21 April 2014 11:02 PM, Felipe Balbi wrote:
>>> Hi,
>>>
>>> On Wed, Mar 26, 2014 at 07:04:45PM -0500, Felipe Balbi wrote:
>>>> this series lets us access the newer registers introduced
>>>> back in OMAP4 which give us some valid information about
>>>> the OMAP HSMMC IP like max block size, support for ADMA,
>>>> support for Retention.
>>>>
>>>> Right now, only setting max_blk_size correctly as supporting
>>>> ADMA and Retention will take a lot of work.
>>>>
>>>> Tested on OMAP5 uEVM.
>>>>
>>>> Felipe Balbi (5):
>>>>    mmc: host: omap_hsmmc: pass host as an argument
>>>>    mmc: host: omap_hsmmc: add reg_offset field
>>>>    mmc: host: omap_hsmmc: introduce new accessor functions
>>>>    mmc: host: omap_hsmmc: switch over to new accessors
>>>>    mmc: host: omap_hsmmc: set max_blk_size correctly
>>
>> Got mislead by your reply to this series, about the alternative way of
>> reading memory size from CAPA register
>
> sure, we can do that if you prefer, I just felt I wouldn't touch
 > platforms I can't really test :-s

I think so, since those 3 newer registers are not documented for all platforms.
Not sure whether it is valid in those cases where it is not documented.

Since capa register has these info and can be
applied uniformly across all paltforms, I feel reading capa register is the
way to go. Do you still think there is a need for new api with no offset ?

>
>>> this has been here for almost a month, any comments ?
>>>
>>
>> Do you see any performance impact with this series ?
>
> in the normal case ? no... it helps only with large transfers
>

Do you have the numbers ?
Is it for read or write,
how large should the transfer size be ?

I couldn't get any performance improvements with this patch series,
Could you please share your test setup, may be I am missing something.

Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 2324 bytes --]

On Thu, Apr 24, 2014 at 08:51:25PM +0530, Balaji T K wrote:
> On Tuesday 22 April 2014 09:18 PM, Felipe Balbi wrote:
> >Hi,
> >
> >On Tue, Apr 22, 2014 at 09:00:12PM +0530, Balaji T K wrote:
> >>On Monday 21 April 2014 11:02 PM, Felipe Balbi wrote:
> >>>Hi,
> >>>
> >>>On Wed, Mar 26, 2014 at 07:04:45PM -0500, Felipe Balbi wrote:
> >>>>this series lets us access the newer registers introduced
> >>>>back in OMAP4 which give us some valid information about
> >>>>the OMAP HSMMC IP like max block size, support for ADMA,
> >>>>support for Retention.
> >>>>
> >>>>Right now, only setting max_blk_size correctly as supporting
> >>>>ADMA and Retention will take a lot of work.
> >>>>
> >>>>Tested on OMAP5 uEVM.
> >>>>
> >>>>Felipe Balbi (5):
> >>>>   mmc: host: omap_hsmmc: pass host as an argument
> >>>>   mmc: host: omap_hsmmc: add reg_offset field
> >>>>   mmc: host: omap_hsmmc: introduce new accessor functions
> >>>>   mmc: host: omap_hsmmc: switch over to new accessors
> >>>>   mmc: host: omap_hsmmc: set max_blk_size correctly
> >>
> >>Got mislead by your reply to this series, about the alternative way of
> >>reading memory size from CAPA register
> >
> >sure, we can do that if you prefer, I just felt I wouldn't touch
> > platforms I can't really test :-s
> 
> I think so, since those 3 newer registers are not documented for all platforms.
> Not sure whether it is valid in those cases where it is not documented.
> 
> Since capa register has these info and can be applied uniformly across
> all paltforms, I feel reading capa register is the way to go. Do you
> still think there is a need for new api with no offset ?

that same HWINFO register gives you information about availability of
ADMA or not.

> >>>this has been here for almost a month, any comments ?
> >>>
> >>
> >>Do you see any performance impact with this series ?
> >
> >in the normal case ? no... it helps only with large transfers
> >
> 
> Do you have the numbers ?
> Is it for read or write,
> how large should the transfer size be ?

no numbers available... didn't save anything.

> I couldn't get any performance improvements with this patch series,
> Could you please share your test setup, may be I am missing something.

just OMAP5 uEVM with UHS-I memory card.

-- 
balbi

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Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Balaji T K]

On Thursday 27 March 2014 05:34 AM, Felipe Balbi wrote:
> Hi,
>
> this series lets us access the newer registers introduced
> back in OMAP4 which give us some valid information about
> the OMAP HSMMC IP like max block size, support for ADMA,
> support for Retention.

"Support for Retention" looks interesting, can you shed more lights
on it

>
> Right now, only setting max_blk_size correctly as supporting
> ADMA and Retention will take a lot of work.
>
> Tested on OMAP5 uEVM.
>
> Felipe Balbi (5):
>    mmc: host: omap_hsmmc: pass host as an argument
>    mmc: host: omap_hsmmc: add reg_offset field
>    mmc: host: omap_hsmmc: introduce new accessor functions
>    mmc: host: omap_hsmmc: switch over to new accessors
>    mmc: host: omap_hsmmc: set max_blk_size correctly
>
>   drivers/mmc/host/omap_hsmmc.c | 291 ++++++++++++++++++++++++++----------------
>   1 file changed, 182 insertions(+), 109 deletions(-)
>

Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Felipe Balbi]

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On Thu, Apr 24, 2014 at 08:01:19PM +0530, Balaji T K wrote:
> On Thursday 27 March 2014 05:34 AM, Felipe Balbi wrote:
> >Hi,
> >
> >this series lets us access the newer registers introduced
> >back in OMAP4 which give us some valid information about
> >the OMAP HSMMC IP like max block size, support for ADMA,
> >support for Retention.
> 
> "Support for Retention" looks interesting, can you shed more lights on
> it

HWINFO has a bit (bit 6) which tells you whether retention is supported,
it's in all TRMs since OMAP3630 or so.

"6	RERETMODE		Retention mode generic parameter
				This bit field indicates whether the
				retention mode is supported using the
				pin PIRFFRET.

				0x0: Retention mode disabled
				0x1: Retention mode enabled"

-- 
balbi

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Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Balaji T K]

On Thursday 24 April 2014 08:09 PM, Felipe Balbi wrote:
> On Thu, Apr 24, 2014 at 08:01:19PM +0530, Balaji T K wrote:
>> On Thursday 27 March 2014 05:34 AM, Felipe Balbi wrote:
>>> Hi,
>>>
>>> this series lets us access the newer registers introduced
>>> back in OMAP4 which give us some valid information about
>>> the OMAP HSMMC IP like max block size, support for ADMA,
>>> support for Retention.
>>
>> "Support for Retention" looks interesting, can you shed more lights on
>> it
>
> HWINFO has a bit (bit 6) which tells you whether retention is supported,
> it's in all TRMs since OMAP3630 or so.
>
> "6	RERETMODE		Retention mode generic parameter
> 				This bit field indicates whether the
> 				retention mode is supported using the
> 				pin PIRFFRET.
>
> 				0x0: Retention mode disabled
> 				0x1: Retention mode enabled"
>

I have seen that but just wondering how the driver can make use of it :-)

Re: [PATCH 0/5] mmc: host: omap_hsmmc: a few improvements

[Felipe Balbi]

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On Thu, Apr 24, 2014 at 08:13:16PM +0530, Balaji T K wrote:
> On Thursday 24 April 2014 08:09 PM, Felipe Balbi wrote:
> >On Thu, Apr 24, 2014 at 08:01:19PM +0530, Balaji T K wrote:
> >>On Thursday 27 March 2014 05:34 AM, Felipe Balbi wrote:
> >>>Hi,
> >>>
> >>>this series lets us access the newer registers introduced
> >>>back in OMAP4 which give us some valid information about
> >>>the OMAP HSMMC IP like max block size, support for ADMA,
> >>>support for Retention.
> >>
> >>"Support for Retention" looks interesting, can you shed more lights on
> >>it
> >
> >HWINFO has a bit (bit 6) which tells you whether retention is supported,
> >it's in all TRMs since OMAP3630 or so.
> >
> >"6	RERETMODE		Retention mode generic parameter
> >				This bit field indicates whether the
> >				retention mode is supported using the
> >				pin PIRFFRET.
> >
> >				0x0: Retention mode disabled
> >				0x1: Retention mode enabled"
> >
> 
> I have seen that but just wondering how the driver can make use of it
> :-)

oh, perhaps you can use to conditionally save context. The difficulty is
knowing if we're going to RET or OFF, but that could be extrapolated
from pm_qos, perhaps ?!?

just a thought.

-- 
balbi

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