From: "Zhu, Lejun" <lejun.zhu@linux.intel.com>
To: "Daniel Glöckner" <dg@emlix.com>, aaron.lu@intel.com
Cc: linus.walleij@linaro.org, gnurou@gmail.com,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
bin.yang@intel.com
Subject: Re: gpio: Add support for Intel SoC PMIC (Crystal Cove)
Date: Mon, 19 May 2014 09:46:18 +0800 [thread overview]
Message-ID: <5379626A.9020203@linux.intel.com> (raw)
In-Reply-To: <20140516174619.GA1471@emlix.com>
On 5/17/2014 1:46 AM, Daniel Glöckner wrote:
> Hi Lejun,
>
> On Wed, May 14, 2014 at 11:44:07PM +0800, Zhu, Lejun wrote:
>> This patch adds support for the GPIO function in Crystal Cove.
>
> in our device ACPI makes use of "virtual" GPIOs that have numbers from
> 0x20 to 0x5E to change various bits in the PMIC. Do you know if this
> is officially supported by the INT33FD ACPI device or if it is a
> vendor hack?
>
> Daniel
>
Hi, sorry I'm quite familiar with ACPI. I know Aaron is looking at the
possibility to use these pins in Linux ACPI, but so far we don't have
any code.
Best Regards
Lejun
next prev parent reply other threads:[~2014-05-19 1:46 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-14 15:44 [PATCH] gpio: Add support for Intel SoC PMIC (Crystal Cove) Zhu, Lejun
2014-05-16 17:33 ` Linus Walleij
2014-05-19 0:27 ` Zhu, Lejun
2014-05-19 14:13 ` Mathias Nyman
2014-05-20 9:16 ` Zhu, Lejun
2014-05-16 17:46 ` Daniel Glöckner
2014-05-19 1:46 ` Zhu, Lejun [this message]
2014-05-17 14:37 ` [PATCH] " Alexandre Courbot
2014-05-19 0:28 ` Zhu, Lejun
2014-05-27 9:01 ` Linus Walleij
2014-05-19 10:39 ` Mika Westerberg
2014-05-20 8:30 ` Mika Westerberg
2014-05-20 9:15 ` Zhu, Lejun
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