Re: balance storm

Peter Zijlstra
2014-05-28T10:30:46Z

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On Wed, May 28, 2014 at 11:08:40AM +0200, Thomas Gleixner wrote:
> On Wed, 28 May 2014, Libo Chen wrote:
>
> > On 2014/5/28 9:53, Mike Galbraith wrote:
> > > On Wed, 2014-05-28 at 09:04 +0800, Libo Chen wrote:
> > >
> > >> oh yes, no tsc only hpet in my box.
> > >
> > > Making poor E5-2658 box a crippled wreck.
> >
> > yes,it is. But cpu usage will be down from 15% to 5% when binding
> > cpu, so maybe read_hpet is not the root cause.
>
> Definitely hpet _IS_ the root cause on a machine as large as this,
> simply because everything gets serialized on the hpet access.
>
> Binding stuff to cpus just makes the timing behaviour different, so
> the hpet serialization is not that prominent, but still bad enough.
>
> Talk to your HW/BIOS vendor. The kernel cannot do anything about
> defunct hardware.

---
Subject: x86: FW_BUG when the TSC goes funny on hardware where it really should be stable

It happens far too often on 'consumer' grade hardware, and sometimes on
'enterprise' too that the TSC gets marked unstable due to FW fuckage,
complain more loudly in this case.

Signed-off-by: Peter Zijlstra <peterz@infradead.org>
---
arch/x86/include/asm/tsc.h | 1 +
arch/x86/kernel/cpu/amd.c | 4 +++-
arch/x86/kernel/cpu/intel.c | 4 +++-
arch/x86/kernel/tsc.c | 7 +++++++
4 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 94605c0e9cee..e33853ee0416 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -52,6 +52,7 @@ extern int check_tsc_unstable(void);
extern int check_tsc_disabled(void);
extern unsigned long native_calibrate_tsc(void);

+extern int tsc_should_be_reliable;
extern int tsc_clocksource_reliable;

/*
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index ce8b8ff0e0ef..46012d2ca5a1 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -483,8 +483,10 @@ static void early_init_amd(struct cpuinfo_x86 *c)
if (c->x86_power & (1 << 8)) {
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
- if (!check_tsc_unstable())
+ if (!check_tsc_unstable()) {
+ tsc_should_be_reliable = 1;
set_sched_clock_stable();
+ }
}

#ifdef CONFIG_X86_64
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index a80029035bf2..2273ca1166bc 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -88,8 +88,10 @@ static void early_init_intel(struct cpuinfo_x86 *c)
if (c->x86_power & (1 << 8)) {
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
- if (!check_tsc_unstable())
+ if (!check_tsc_unstable()) {
+ tsc_should_be_reliable = 1;
set_sched_clock_stable();
+ }
}

/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 57e5ce126d5a..1f93827561d8 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -40,6 +40,7 @@ static int __read_mostly tsc_disabled = -1;

static struct static_key __use_tsc = STATIC_KEY_INIT;

+int tsc_should_be_reliable;
int tsc_clocksource_reliable;

/*
@@ -994,6 +995,12 @@ void mark_tsc_unstable(char *reason)
clear_sched_clock_stable();
disable_sched_clock_irqtime();
pr_info("Marking TSC unstable due to %s\n", reason);
+
+ if (tsc_should_be_reliable) {
+ pr_err(FW_BUG "TSC unstable even though it should be; "
+ "HW/BIOS broken, contact your vendor.\n");
+ }
+
/* Change only the rating, when not registered */
if (clocksource_tsc.mult)
clocksource_mark_unstable(&clocksource_tsc);

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