Re: PATCH[[vme/bridges/vme_ca91cx42.c:1382: Bad if test Bug Fix]‏‏

[Martyn Welch <martyn.welch@ge.com>]

Nick,

Sorry for the delay in responding.

I'm staring at the manual for the ca91c142 and the relevant bits in the 
VSIx_CTL registers definitely need to be set to 0 for A16, likewise with 
the LM_CTL register. The pattern (3<<16) would enable one of the 
"reserved" address spaces.

Martyn

On 12/06/14 15:33, nick wrote:
> Here is the fixed patch. Having issues with using Thunderbird
> so just used Evolution for now.
> Nick
> --- drivers/vme/bridges/vme_ca91cx42.h.orig	2014-06-11 22:50:29.339671939 -0400
> +++ drivers/vme/bridges/vme_ca91cx42.h	2014-06-11 23:15:36.027685173 -0400
> Fixes bug issues with wrong bus width in if statments in vme_ca91cx42.c
> Signed-off-by: Nicholas Krause <nickkrause@sympatico.ca>
> @@ -526,7 +526,7 @@ static const int CA91CX42_LINT_LM[] = {
>   #define CA91CX42_VSI_CTL_SUPER_SUPR	(1<<21)
>
>   #define CA91CX42_VSI_CTL_VAS_M		(7<<16)
> -#define CA91CX42_VSI_CTL_VAS_A16	0
> +#define CA91CX42_VSI_CTL_VAS_A16	(3<<16)
>   #define CA91CX42_VSI_CTL_VAS_A24	(1<<16)
>   #define CA91CX42_VSI_CTL_VAS_A32	(1<<17)
>   #define CA91CX42_VSI_CTL_VAS_USER1	(3<<17)
> @@ -549,7 +549,7 @@ static const int CA91CX42_LINT_LM[] = {
>   #define CA91CX42_LM_CTL_SUPR		(1<<21)
>   #define CA91CX42_LM_CTL_NPRIV		(1<<20)
>   #define CA91CX42_LM_CTL_AS_M		(5<<16)
> -#define CA91CX42_LM_CTL_AS_A16		0
> +#define CA91CX42_LM_CTL_AS_A16		(3<<16)
>   #define CA91CX42_LM_CTL_AS_A24		(1<<16)
>   #define CA91CX42_LM_CTL_AS_A32		(1<<17)
>
>
>

-- 
Martyn Welch (Lead Software Engineer)  | Registered in England and Wales
GE Intelligent Platforms               | (3828642) at 100 Barbirolli Square
T +44(0)1327322748                     | Manchester, M2 3AB
E martyn.welch@ge.com                  | VAT:GB 927559189