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From: Tomeu Vizoso <tomeu.vizoso@collabora.com>
To: Tomasz Figa <tomasz.figa@gmail.com>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Mike Turquette <mturquette@linaro.org>,
	rabin@rab.in, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Subject: Re: [RFC v2 0/5] Per-user clock constraints
Date: Thu, 10 Jul 2014 10:00:44 +0200	[thread overview]
Message-ID: <53BE482C.9000503@collabora.com> (raw)
In-Reply-To: <53BDA31D.40502@gmail.com>

On 07/09/2014 10:16 PM, Tomasz Figa wrote:
> Hi Tomeu,
>
> On 03.07.2014 16:38, Tomeu Vizoso wrote:
>> Hello,
>>
>> here is another round for commenting, not very different from the first one.
>>
>> Something I forgot to mention before is that the function rename was performed
>> by the scripts in:
>>
>> http://cgit.collabora.com/git/user/tomeu/linux.git/commit/?h=clk-refactoring-4&id=0e983e28864229f2cd525f87d59e034c4876b233
>>
>> As before, I have only checked that drivers/clk/ builds with allyesconfig, and
>> that a kernel can be built for tegra_defconfig.
>
> This is quite an interesting series. I have reviewed two of five patches
> and have plans to look at remaining ones, however here are few general
> issues I'd like to raise:
>
> - somehow I don't see patch 2/5 on LAKML. Too big?

Yes, I'm not sure what I can do about that, but it's only automated 
function renaming. I'm going to send v3 in a bit and will CC you.

> - I see the series changing particular clock drivers. A good practice
> would be to Cc respective driver maintainers to take a look at those
> changes.

Now that I'm more confident about this approach, for the next version 
I'm going to CC them as well.

> - please make sure that all the patches don't have checkpatch errors or
> significant warnings.

Sure.

> Will try (myself or by asking someone else) to do some testing on
> Samsung platforms.

That will be great, thanks. One scenario I'm looking forward to test 
this with is low system load while the display is being updated often at 
a high resolution.

I would expect to see that the Exynos5 devfreq driver sets a relatively 
low floor frequency, and the DC driver overrides that by setting a 
higher floor, based on the calculated bandwidth that will be required to 
move pixels around.

Regards,

Tomeu

> Best regards,
> Tomasz
>


      reply	other threads:[~2014-07-10  8:00 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-03 14:38 [RFC v2 0/5] Per-user clock constraints Tomeu Vizoso
2014-07-03 14:38 ` [RFC v2 1/5] clk: Add temporary mapping to the existing API Tomeu Vizoso
2014-07-03 14:38 ` [RFC v2 2/5] clk: Move all drivers to use internal API Tomeu Vizoso
2014-07-03 14:38 ` [RFC v2 3/5] clk: use struct clk only for external API Tomeu Vizoso
2014-07-09 19:27   ` Tomasz Figa
2014-07-10  9:13     ` Tomeu Vizoso
2014-07-09 20:12   ` Tomasz Figa
2014-07-10  9:16     ` Tomeu Vizoso
2014-07-03 14:38 ` [RFC v2 4/5] clk: per-user clock accounting for debug Tomeu Vizoso
2014-07-09 20:01   ` Tomasz Figa
2014-07-10 10:51     ` Tomeu Vizoso
2014-07-03 14:38 ` [RFC v2 5/5] clk: Add floor and ceiling constraints to clock rates Tomeu Vizoso
2014-07-09 20:16 ` [RFC v2 0/5] Per-user clock constraints Tomasz Figa
2014-07-10  8:00   ` Tomeu Vizoso [this message]

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