From: Alexandre Courbot <acourbot@nvidia.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Ben Skeggs <bskeggs@redhat.com>, David Airlie <airlied@linux.ie>,
David Herrmann <dh.herrmann@gmail.com>,
Lucas Stach <dev@lynxeye.de>,
Thierry Reding <thierry.reding@gmail.com>,
Maarten Lankhorst <maarten.lankhorst@canonical.com>,
<nouveau@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>, <linux-tegra@vger.kernel.org>,
Alexandre Courbot <gnurou@gmail.com>
Subject: Re: [Nouveau] [PATCH v4 4/6] drm/nouveau: synchronize BOs when required
Date: Fri, 11 Jul 2014 18:35:16 +0900 [thread overview]
Message-ID: <53BFAFD4.5040401@nvidia.com> (raw)
In-Reply-To: <20140711074138.GW17271@phenom.ffwll.local>
On 07/11/2014 04:41 PM, Daniel Vetter wrote:
> On Fri, Jul 11, 2014 at 11:40:27AM +0900, Alexandre Courbot wrote:
>> On 07/10/2014 10:04 PM, Daniel Vetter wrote:
>>> On Tue, Jul 08, 2014 at 05:25:59PM +0900, Alexandre Courbot wrote:
>>>> On architectures for which access to GPU memory is non-coherent,
>>>> caches need to be flushed and invalidated explicitly when BO control
>>>> changes between CPU and GPU.
>>>>
>>>> This patch adds buffer synchronization functions which invokes the
>>>> correct API (PCI or DMA) to ensure synchronization is effective.
>>>>
>>>> Based on the TTM DMA cache helper patches by Lucas Stach.
>>>>
>>>> Signed-off-by: Lucas Stach <dev@lynxeye.de>
>>>> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
>>>> ---
>>>> drivers/gpu/drm/nouveau/nouveau_bo.c | 56 +++++++++++++++++++++++++++++++++++
>>>> drivers/gpu/drm/nouveau/nouveau_bo.h | 2 ++
>>>> drivers/gpu/drm/nouveau/nouveau_gem.c | 12 ++++++++
>>>> 3 files changed, 70 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
>>>> index 67e9e8e2e2ec..47e4e8886769 100644
>>>> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
>>>> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
>>>> @@ -402,6 +402,60 @@ nouveau_bo_unmap(struct nouveau_bo *nvbo)
>>>> ttm_bo_kunmap(&nvbo->kmap);
>>>> }
>>>>
>>>> +void
>>>> +nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
>>>> +{
>>>> + struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
>>>> + struct nouveau_device *device = nouveau_dev(drm->dev);
>>>> + struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
>>>> + int i;
>>>> +
>>>> + if (!ttm_dma)
>>>> + return;
>>>> +
>>>> + if (nv_device_is_cpu_coherent(device) || nvbo->force_coherent)
>>>> + return;
>>>
>>> Is the is_cpu_coherent check really required? On coherent platforms the
>>> sync_for_foo should be a noop. It's the dma api's job to encapsulate this
>>> knowledge so that drivers can be blissfully ignorant. The explicit
>>> is_coherent check makes this a bit leaky. And same comment that underlying
>>> the bus-specifics dma-mapping functions are identical.
>>
>> I think you are right, the is_cpu_coherent check should not be needed here.
>> I still think we should have separate paths for the PCI/DMA cases though,
>> unless you can point me to a source that clearly states that the PCI API is
>> deprecated and that DMA should be used instead.
>
> Ah, on 2nd look I've found it again. Quoting
> Documentation/DMA-API-HOWTO.txt:
>
> "Note that the DMA API works with any bus independent of the underlying
> microprocessor architecture. You should use the DMA API rather than the
> bus-specific DMA API, i.e., use the dma_map_*() interfaces rather than the
> pci_map_*() interfaces."
>
> The advice is fairly strong here I think ;-) And imo the idea makes sense,
> since it allows drivers like nouveau here to care much less about the
> actual bus used to get data to/from the ip block. And if you look at intel
> gfx it makes even more sense since the pci layer we have is really just a
> thin fake shim whacked on top of the hw (on SoCs at least).
Indeed, I stand corrected. :) That's good news actually, as it will
simplify the code. Thanks for pointing that out!
I will send a new revision that makes use of the DMA API exclusively and
will remove the nv_device_map/unmap() functions which are pretty useless
now.
next prev parent reply other threads:[~2014-07-11 9:35 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-08 8:25 [PATCH v4 0/6] drm: nouveau: memory coherency on ARM Alexandre Courbot
2014-07-08 8:25 ` [PATCH v4 1/6] drm/ttm: expose CPU address of DMA-allocated pages Alexandre Courbot
2014-07-08 8:25 ` [PATCH v4 2/6] drm/nouveau: map pages using DMA API on platform devices Alexandre Courbot
2014-07-10 12:58 ` [Nouveau] " Daniel Vetter
2014-07-11 2:35 ` Alexandre Courbot
2014-07-11 2:50 ` Ben Skeggs
2014-07-11 2:57 ` Alexandre Courbot
2014-07-11 9:53 ` Lucas Stach
2014-07-11 7:38 ` Daniel Vetter
2014-07-08 8:25 ` [PATCH v4 3/6] drm/nouveau: introduce nv_device_is_cpu_coherent() Alexandre Courbot
2014-07-08 8:25 ` [PATCH v4 4/6] drm/nouveau: synchronize BOs when required Alexandre Courbot
2014-07-10 13:04 ` [Nouveau] " Daniel Vetter
2014-07-11 2:40 ` Alexandre Courbot
2014-07-11 7:41 ` Daniel Vetter
2014-07-11 9:35 ` Alexandre Courbot [this message]
2014-07-08 8:26 ` [PATCH v4 5/6] drm/nouveau: implement explicitly coherent BOs Alexandre Courbot
2014-07-08 8:26 ` [PATCH v4 6/6] drm/nouveau: allocate GPFIFOs and fences coherently Alexandre Courbot
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