[PATCH v2 6/7] perf, x86: enable large PEBS interrupt threshold for SNB/IVB/HSW

Yan, Zheng
2014-07-15T08:59:43Z

Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index cb5a838..dba03b3 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2456,6 +2456,7 @@ __init int intel_pmu_init(void)
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);

+ x86_pmu.multi_pebs = true;
pr_cont("SandyBridge events, ");
break;
case 58: /* IvyBridge */
@@ -2484,6 +2485,7 @@ __init int intel_pmu_init(void)
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);

+ x86_pmu.multi_pebs = true;
pr_cont("IvyBridge events, ");
break;

@@ -2511,6 +2513,8 @@ __init int intel_pmu_init(void)
x86_pmu.get_event_constraints = hsw_get_event_constraints;
x86_pmu.cpu_events = hsw_events_attrs;
x86_pmu.lbr_double_abort = true;
+
+ x86_pmu.multi_pebs = true;
pr_cont("Haswell events, ");
break;

--
1.9.3