[PATCH v4 0/4] Patches to add support for Rockchip dwc2 controller

[PATCH v4 0/4] Patches to add support for Rockchip dwc2 controller

[Kever Yang]

These patches to add support for dwc2 controller found in
Rockchip processors rk3066, rk3188 and rk3288,
and enable dts for rk3288 evb.

Changes in v4:
- max_transfer_size change to 65536, this should be enough
  for most transfer, the hardware auto-detect will set this
  to 0x7ffff which may make dma_alloc_coherent fail when
  non-dword aligned buf from driver like usbnet happen.
- remove EHCI and HSIC dts patch for Doug had post it seprately.

Changes in v3:
- EHCI and HSIC move new for version 3.
- Rebase

Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2

Kever Yang (4):
  Documentation: dt-bindings: add dt binding info for Rockchip dwc2
  usb: dwc2: add compatible data for rockchip soc
  ARM: dts: add rk3288 dwc2 controller support
  ARM: dts: Enable USB otg and host1(dwc) on rk3288-evb

 Documentation/devicetree/bindings/usb/dwc2.txt |  3 +++
 arch/arm/boot/dts/rk3288-evb.dtsi              |  6 ++++++
 arch/arm/boot/dts/rk3288.dtsi                  | 20 ++++++++++++++++++
 drivers/usb/dwc2/platform.c                    | 29 ++++++++++++++++++++++++++
 4 files changed, 58 insertions(+)

-- 
1.9.1

[PATCH v4 1/4] Documentation: dt-bindings: add dt binding info for Rockchip dwc2

[Kever Yang]

This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info

 Documentation/devicetree/bindings/usb/dwc2.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 467ddd1..2899679 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -4,6 +4,9 @@ Platform DesignWare HS OTG USB 2.0 controller
 Required properties:
 - compatible : One of:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
+  - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
+  - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
   - snps,dwc2: A generic DWC2 USB controller with default parameters.
 - reg : Should contain 1 register range (address and length)
 - interrupts : Should contain 1 interrupt
-- 
1.9.1

[PATCH v4 2/4] usb: dwc2: add compatible data for rockchip soc

[Kever Yang]

This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Paul Zimmerman <paulz@synopsys.com>
---

Changes in v4:
- max_transfer_size change to 65536, this should be enough
  for most transfer, the hardware auto-detect will set this
  to 0x7ffff which may make dma_alloc_coherent fail when
  non-dword aligned buf from driver like usbnet happen.

Changes in v3: None
Changes in v2:
- set most parameters as driver auto-detect

 drivers/usb/dwc2/platform.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index a10e7a3..832b103 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -75,6 +75,34 @@ static const struct dwc2_core_params params_bcm2835 = {
 	.uframe_sched			= 0,
 };
 
+static const struct dwc2_core_params params_rk3066 = {
+	.otg_cap			= 2,	/* non-HNP/non-SRP */
+	.otg_ver			= -1,
+	.dma_enable			= -1,
+	.dma_desc_enable		= 0,
+	.speed				= -1,
+	.enable_dynamic_fifo		= 1,
+	.en_multiple_tx_fifo		= -1,
+	.host_rx_fifo_size		= 520,	/* 520 DWORDs */
+	.host_nperio_tx_fifo_size	= 128,	/* 128 DWORDs */
+	.host_perio_tx_fifo_size	= 256,	/* 256 DWORDs */
+	.max_transfer_size		= 65536,
+	.max_packet_count		= -1,
+	.host_channels			= -1,
+	.phy_type			= -1,
+	.phy_utmi_width			= -1,
+	.phy_ulpi_ddr			= -1,
+	.phy_ulpi_ext_vbus		= -1,
+	.i2c_enable			= -1,
+	.ulpi_fs_ls			= -1,
+	.host_support_fs_ls_low_power	= -1,
+	.host_ls_low_power_phy_clk	= -1,
+	.ts_dline			= -1,
+	.reload_ctl			= -1,
+	.ahbcfg				= 0x7, /* INCR16 */
+	.uframe_sched			= -1,
+};
+
 /**
  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
  * DWC_otg driver
@@ -97,6 +125,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
 
 static const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
+	{ .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 	{ .compatible = "snps,dwc2", .data = NULL },
 	{},
 };
-- 
1.9.1

RE: [PATCH v4 2/4] usb: dwc2: add compatible data for rockchip soc

[Paul Zimmerman]

> From: Kever Yang [mailto:kever.yang@gmail.com] On Behalf Of Kever Yang
> Sent: Thursday, August 07, 2014 2:35 AM
> 
> This patch add compatible data for dwc2 controller found on
> rk3066, rk3188 and rk3288 processors from rockchip.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Paul Zimmerman <paulz@synopsys.com>
> ---
> 
> Changes in v4:
> - max_transfer_size change to 65536, this should be enough
>   for most transfer, the hardware auto-detect will set this
>   to 0x7ffff which may make dma_alloc_coherent fail when
>   non-dword aligned buf from driver like usbnet happen.

Hi Kever,

Did you test this change thoroughly? I have vague memories of any
value above 65535 causing problems, at least on my hardware. And I
see it is set to 65535 in both pci.c and platform.c. I could be
wrong, but I thought I should mention it.

-- 
Paul

Re: [PATCH v4 2/4] usb: dwc2: add compatible data for rockchip soc

[Doug Anderson]

Paul,

On Thu, Aug 7, 2014 at 11:26 AM, Paul Zimmerman
<Paul.Zimmerman@synopsys.com> wrote:
>> From: Kever Yang [mailto:kever.yang@gmail.com] On Behalf Of Kever Yang
>> Sent: Thursday, August 07, 2014 2:35 AM
>>
>> This patch add compatible data for dwc2 controller found on
>> rk3066, rk3188 and rk3288 processors from rockchip.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> Acked-by: Paul Zimmerman <paulz@synopsys.com>
>> ---
>>
>> Changes in v4:
>> - max_transfer_size change to 65536, this should be enough
>>   for most transfer, the hardware auto-detect will set this
>>   to 0x7ffff which may make dma_alloc_coherent fail when
>>   non-dword aligned buf from driver like usbnet happen.
>
> Hi Kever,
>
> Did you test this change thoroughly? I have vague memories of any
> value above 65535 causing problems, at least on my hardware. And I
> see it is set to 65535 in both pci.c and platform.c. I could be
> wrong, but I thought I should mention it.

Certainly it is documented in the header file to have a max of 65535:

 * @max_transfer_size:  The maximum transfer size supported, in bytes
 *                       2047 to 65,535
 *                      Actual maximum value is autodetected and also
 *                      the default.

...but looking at the register definition that I see, the size can be
up to 19 bits.  A 19-bit transfer far exceeds 65535.  Do you remember
what the error was?  Certainly I can imagine there being errors with
large calls to dma_alloc_coherent()...

I know that with Kever's change I can do USB Ethernet downloads, so it
is at least working to some degree.  ...to me it feels like Kever
should resubmit with 65535 (to match the documentation) and then work
in the background to figure out what the max_transfer_size really
ought to be.

-Doug

RE: [PATCH v4 2/4] usb: dwc2: add compatible data for rockchip soc

[Paul Zimmerman]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 2135 bytes --]

> From: dianders@google.com [mailto:dianders@google.com] On Behalf Of Doug Anderson
> Sent: Thursday, August 07, 2014 1:53 PM
> 
> On Thu, Aug 7, 2014 at 11:26 AM, Paul Zimmerman
> <Paul.Zimmerman@synopsys.com> wrote:
> >> From: Kever Yang [mailto:kever.yang@gmail.com] On Behalf Of Kever Yang
> >> Sent: Thursday, August 07, 2014 2:35 AM
> >>
> >> This patch add compatible data for dwc2 controller found on
> >> rk3066, rk3188 and rk3288 processors from rockchip.
> >>
> >> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> >> Acked-by: Paul Zimmerman <paulz@synopsys.com>
> >> ---
> >>
> >> Changes in v4:
> >> - max_transfer_size change to 65536, this should be enough
> >>   for most transfer, the hardware auto-detect will set this
> >>   to 0x7ffff which may make dma_alloc_coherent fail when
> >>   non-dword aligned buf from driver like usbnet happen.
> >
> > Hi Kever,
> >
> > Did you test this change thoroughly? I have vague memories of any
> > value above 65535 causing problems, at least on my hardware. And I
> > see it is set to 65535 in both pci.c and platform.c. I could be
> > wrong, but I thought I should mention it.
> 
> Certainly it is documented in the header file to have a max of 65535:
> 
>  * @max_transfer_size:  The maximum transfer size supported, in bytes
>  *                       2047 to 65,535
>  *                      Actual maximum value is autodetected and also
>  *                      the default.
> 
> ...but looking at the register definition that I see, the size can be
> up to 19 bits.  A 19-bit transfer far exceeds 65535.  Do you remember
> what the error was?  Certainly I can imagine there being errors with
> large calls to dma_alloc_coherent()...

It's pretty fuzzy. I think a certain type of transfer (Isoc?) didn't
work. But I may be misremembering, the problem could have been with
max_packet_count > 255 instead. If you have tested it thoroughly with
different types of devices then it's probably OK.

-- 
Paul

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Re: [PATCH v4 2/4] usb: dwc2: add compatible data for rockchip soc

[Kever.Yang]

On 08/08/2014 04:52 AM, Doug Anderson wrote:
> Paul,
>
> On Thu, Aug 7, 2014 at 11:26 AM, Paul Zimmerman
> <Paul.Zimmerman@synopsys.com> wrote:
>>> From: Kever Yang [mailto:kever.yang@gmail.com] On Behalf Of Kever Yang
>>> Sent: Thursday, August 07, 2014 2:35 AM
>>>
>>> This patch add compatible data for dwc2 controller found on
>>> rk3066, rk3188 and rk3288 processors from rockchip.
>>>
>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>>> Acked-by: Paul Zimmerman <paulz@synopsys.com>
>>> ---
>>>
>>> Changes in v4:
>>> - max_transfer_size change to 65536, this should be enough
>>>    for most transfer, the hardware auto-detect will set this
>>>    to 0x7ffff which may make dma_alloc_coherent fail when
>>>    non-dword aligned buf from driver like usbnet happen.
>> Hi Kever,
>>
>> Did you test this change thoroughly? I have vague memories of any
>> value above 65535 causing problems, at least on my hardware. And I
>> see it is set to 65535 in both pci.c and platform.c. I could be
>> wrong, but I thought I should mention it.
> Certainly it is documented in the header file to have a max of 65535:
>
>   * @max_transfer_size:  The maximum transfer size supported, in bytes
>   *                       2047 to 65,535
>   *                      Actual maximum value is autodetected and also
>   *                      the default.
Sorry for didn't check the header file, I'll change it to 65535 and 
resubmit.
>
> ...but looking at the register definition that I see, the size can be
> up to 19 bits.  A 19-bit transfer far exceeds 65535.  Do you remember
> what the error was?  Certainly I can imagine there being errors with
> large calls to dma_alloc_coherent()...
>
> I know that with Kever's change I can do USB Ethernet downloads, so it
> is at least working to some degree.  ...to me it feels like Kever
> should resubmit with 65535 (to match the documentation) and then work
> in the background to figure out what the max_transfer_size really
> ought to be.
You are right.
> -Doug
>
>
>

Re: [PATCH v4 2/4] usb: dwc2: add compatible data for rockchip soc

[Kever Yang]

Paul,

On 08/08/2014 02:26 AM, Paul Zimmerman wrote:
>> From: Kever Yang [mailto:kever.yang@gmail.com] On Behalf Of Kever Yang
>> Sent: Thursday, August 07, 2014 2:35 AM
>>
>> This patch add compatible data for dwc2 controller found on
>> rk3066, rk3188 and rk3288 processors from rockchip.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> Acked-by: Paul Zimmerman <paulz@synopsys.com>
>> ---
>>
>> Changes in v4:
>> - max_transfer_size change to 65536, this should be enough
>>    for most transfer, the hardware auto-detect will set this
>>    to 0x7ffff which may make dma_alloc_coherent fail when
>>    non-dword aligned buf from driver like usbnet happen.
> Hi Kever,
>
> Did you test this change thoroughly? I have vague memories of any
> value above 65535 causing problems, at least on my hardware. And I
> see it is set to 65535 in both pci.c and platform.c. I could be
> wrong, but I thought I should mention it.
I test it on rk3288 evb, it works find with 65536, I'm sorry for didn't 
mention it in my patch.
The problem in my platform is if the value use hardware auto-detect, it 
will be 0x7ffff,
and that will cause the dma_alloc_coherent fail in hcd driver.

The value less than 0x7ffff should be fine for hardware, but for the 
software, it depends on
how we use it.

What kind of problem did you met? Software problem or hardware problem? 
Maybe I should
pay more attention for this value. :)

>

[PATCH v4 3/4] ARM: dts: add rk3288 dwc2 controller support

[Kever Yang]

rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.

Controller can works with usb PHY default setting and Vbus on.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

---

Changes in v4: None
Changes in v3:
- EHCI and HSIC move new for version 3.

Changes in v2: None

 arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index e7cb008..9713054 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -156,6 +156,26 @@
 		status = "disabled";
 	};
 
+	usb_host1: usb@ff540000 {
+		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+				"snps,dwc2";
+		reg = <0xff540000 0x40000>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_USBHOST1>;
+		clock-names = "otg";
+		status = "disabled";
+	};
+
+	usb_otg: usb@ff580000 {
+		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+				"snps,dwc2";
+		reg = <0xff580000 0x40000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_OTG0>;
+		clock-names = "otg";
+		status = "disabled";
+	};
+
 	uart2: serial@ff690000 {
 		compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 		reg = <0xff690000 0x100>;
-- 
1.9.1

Re: [PATCH v4 3/4] ARM: dts: add rk3288 dwc2 controller support

[Doug Anderson]

Kever,

On Thu, Aug 7, 2014 at 2:34 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
> rk3288 has two kind of usb controller, this add the dwc2 controller
> for otg and host1.
>
> Controller can works with usb PHY default setting and Vbus on.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>
> ---
>
> Changes in v4: None
> Changes in v3:
> - EHCI and HSIC move new for version 3.
>
> Changes in v2: None
>
>  arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)

This looks good to me.  I haven't been able to personally test the OTG
port (since my board doesn't have vbus wired), but I've tested the
Host port.

I would request that you re-sort by base address (ignoring uart2,
which apparently is in the wrong place).  Please make sure you base
atop my patch that fixes the sort order of OHCI and EHCI.  I think
that's supposed to land any day now.

After changing the sort order:

Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>

[PATCH v4 4/4] ARM: dts: Enable USB otg and host1(dwc) on rk3288-evb

[Kever Yang]

USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

---

Changes in v4: None
Changes in v3:
- Rebase

Changes in v2:
- evb patch added in version 2

 arch/arm/boot/dts/rk3288-evb.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 4f57209..a322100 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -94,3 +94,9 @@
 &usb_host0_ehci {
 	status = "okay";
 };
+&usb_host1 {
+	status = "okay";
+};
+&usb_otg {
+	status = "okay";
+};
-- 
1.9.1

Re: [PATCH v4 4/4] ARM: dts: Enable USB otg and host1(dwc) on rk3288-evb

[Doug Anderson]

Kever,

On Thu, Aug 7, 2014 at 2:34 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
> USB otg port is the usb3.0 b-port on the board.
> USB host1 port is the host A port nearby the otg port.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>
> ---
>
> Changes in v4: None
> Changes in v3:
> - Rebase
>
> Changes in v2:
> - evb patch added in version 2
>
>  arch/arm/boot/dts/rk3288-evb.dtsi | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
> index 4f57209..a322100 100644
> --- a/arch/arm/boot/dts/rk3288-evb.dtsi
> +++ b/arch/arm/boot/dts/rk3288-evb.dtsi
> @@ -94,3 +94,9 @@
>  &usb_host0_ehci {
>         status = "okay";
>  };
> +&usb_host1 {
> +       status = "okay";
> +};
> +&usb_otg {
> +       status = "okay";
> +};

Do you really want to enable "usb_otg" on EVB?  I think you have a
rework on your board to enable vbus on this port, but I don't think
it's applicable to anyone else, is it?

I'm told that on some boards you can turn on GPIO0_12 to get vbus, but
I don't have a board like that so I can't really test.  Even so,
before enabling the otg port we should probably put something in the
dts file that would turn on that vbus...

Unless you've somehow gotten gadget mode to work on the OTG port, my
vote would be to leave it disabled for the EVB for now.


NOTE: keeping the otg definition in the main "r3288.dtsi" (patch 3/4)
still makes sense because other boards may have the OTG port hooked
up.


-Doug