Re: [RESEND PATCH 2/2] ARM: dts: Add tps65090 FET constraints on Peach Pit and Pi

Javier Martinez Canillas
2014-08-11T17:31:10Z

Hello Mark,

On 08/11/2014 06:02 PM, Mark Brown wrote:
> On Mon, Aug 11, 2014 at 08:57:24AM -0700, Doug Anderson wrote:
>> On Mon, Aug 11, 2014 at 4:38 AM, Javier Martinez Canillas
>
>> > After the switch is turned on, a safety timer is started
>> > and before this timer times out the output voltage must
>> > have reached the input voltage. Otherwise the switch is
>> > turned off expecting an overload condition.
>
>> > So using the maximum output voltage slew rate and the timer
>> > minimum and maximum timeouts, a voltage constraints can be
>> > expressed as bounded limits for the timeout. That is what
>> > is used in the board schematics and should be in the DT too.
>
>> I don't understand this, but if you and Mark are happy with it...
>
> I have not looked at this change to my knowledge.
>

No worries, I have to re-spin anyways to fix the 17v typo that Doug pointed out.
But basically is related to our previous discussion in patch:

"[RFC 3/5] regulator: core: Only apply constraints if available on list voltage"

where you explained [0] to me that child regulators should explicit set their
constraints instead of getting from its parent supply. So this patch adds the
needed constraints for the children FETs even when their output voltage depend
on its parent supply.

>> ...I'm also not 100% certain what the above description has to do with
>> this change, but I'll admit to having only skimmed some of the earlier
>> conversations.
>
> It's not at all clear to me either looking at the quoted section.
>

Yes, the commit message is not great to say the least. Also I didn't have the
last version of the documentation so I misunderstood from where the constraints
mentioned in the schematics came from. Will fix the commit message when posting v2.

Thanks a lot and best regards,
Javier

[0]: https://lkml.org/lkml/2014/7/30/99