From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754551AbaHKWfN (ORCPT ); Mon, 11 Aug 2014 18:35:13 -0400 Received: from mail-by2lp0244.outbound.protection.outlook.com ([207.46.163.244]:56653 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753054AbaHKWfL (ORCPT ); Mon, 11 Aug 2014 18:35:11 -0400 Message-ID: <53E94517.4090103@caviumnetworks.com> Date: Mon, 11 Aug 2014 15:35:03 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: Sadasivan Shaiju CC: , , , Subject: Re: [PATCH] delaying interrupts in mips [ 2.6.32] References: <5bf77c903d6df6cfe656a3585c314df1@mail.gmail.com> <53E94382.1010203@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.195] X-ClientProxiedBy: BLUPR07CA096.namprd07.prod.outlook.com (25.160.24.51) To BY2PR07MB583.namprd07.prod.outlook.com (10.141.221.155) X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 03008837BD X-Forefront-Antispam-Report: SFV:NSPM;SFS:(6009001)(5423002)(479174003)(377454003)(51704005)(189002)(13464003)(50944004)(199002)(288314003)(24454002)(575784001)(85306004)(36756003)(64706001)(77982001)(83072002)(42186005)(46102001)(33656002)(66066001)(15975445006)(65956001)(80022001)(69596002)(87976001)(102836001)(77096002)(76482001)(53416004)(47776003)(92566001)(59896001)(20776003)(92726001)(4396001)(50466002)(95666004)(107046002)(74662001)(31966008)(74502001)(110136001)(106356001)(81156004)(19580395003)(19580405001)(23676002)(105586002)(83322001)(65806001)(101416001)(83506001)(64126003)(85852003)(79102001)(54356999)(65816999)(99396002)(87266999)(76176999)(81542001)(50986999)(21056001)(80316001)(81342001);DIR:OUT;SFP:;SCL:1;SRVR:BY2PR07MB583;H:dl.caveonetworks.com;FPR:;MLV:sfv;PTR:InfoNoRecords;MX:1;LANG:en; X-OriginatorOrg: caviumnetworks.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/11/2014 03:33 PM, Sadasivan Shaiju wrote: > Hi David, > > Sorry , I didn't check that . I am late in submitting it . OK. Next time try to apply your patch and test it before submitting. David Daney > > Regards, > Shaiju. > > -----Original Message----- > From: David Daney [mailto:ddaney@caviumnetworks.com] > Sent: Monday, August 11, 2014 3:28 PM > To: Sadasivan Shaiju > Cc: linux-kernel@vger.kernel.org; ralf@linux-mips.org; > david.daney@cavium.com; shaiju_sada@yahoo.com > Subject: Re: [PATCH] delaying interrupts in mips [ 2.6.32] > > On 08/11/2014 03:13 PM, Sadasivan Shaiju wrote: >> Hi , >> >> I work for Montavista (Cavium Inc) as a Technical Lead . I want >> to push some of the kernel patches to rt community (2.6.32 kernel >> 2.6.33 rt patch) , so that It will go to the main line These >> patches are reviewed and approved by our system Architect. I >> request you to include in the main line . > > It is already in the "main line": > > commit 1bcfecc028686ea32e49b0f4f6e8a665917cb49a > Author: Yong Zhang > Date: Thu Jul 19 09:13:53 2012 +0200 > > MIPS: Octeon: delay enable irq to ->smp_finish() > > To prepare for smoothing set_cpu_[active|online]() mess up > > Signed-off-by: Yong Zhang > Cc: Sergei Shtylyov > Cc: David Daney > Acked-by: David Daney > Patchwork: https://patchwork.linux-mips.org/patch/3845/ > Signed-off-by: Ralf Baechle > > Why are you sending it again? > > David Daney > > > > These issues were reported by our >> customer CISCO . >> >> Problem Description: >> When CONFIG_DEBUG_PREEMPT is enabled the following stack trace occurs. >> >> [ 170.814470] BUG: using smp_processor_id() in preemptible [00000000] >> code: sirq-timer/4/62 >> [ 170.814482] caller is hrtimer_run_pending+0x10/0x20 [ 170.814488] >> Call Trace: >> [ 170.814496] [] dump_stack+0x8/0x34 [ 170.814507] >> [] debug_smp_processor_id+0xe0/0xf0 [ 170.814517] >> [] hrtimer_run_pending+0x10/0x20 [ 170.814528] >> [] run_timer_softirq+0x60/0x348 [ 170.814539] >> [] run_ksoftirqd+0x1c8/0x348 [ 170.814550] >> [] kthread+0x88/0x90 [ 170.814561] >> [] kernel_thread_helper+0x10/0x18 >> >> Root Cause: >> Interrupt was occurring before the processor was completely up, and >> the softirq threads were unable to schedule on the processor and then >> ran on the wrong CPU. >> >> How Solved: >> Enabling of interrupt has been delayed till smp_finish so that >> kthread_bind can safely bind threads to any possible CPU. >> >> I request you to merge the above patch to the main line . If any >> questions please contact me atsshaiju@mvista.com >> (shaiju_sada@yahoo.com) >> >> Regards, >> Shaiju. >> >> >> 0001-Interrupt-delaying-enabling-of-interrupt.patch >> >> >> From 58512475cba93003c23f2b380b573e64eebcabd5 Mon Sep 17 00:00:00 >> 2001 >> From: Sadasivan Shaiju >> Date: Mon, 20 Feb 2012 13:25:50 -0800 >> Subject: [PATCH] Interrupt : delaying enabling of interrupt >> >> Source: MontaVista Software, LLC >> MR: 47157 >> Type: Defect Fix >> Disposition: Local >> ChangeID: 48c837329556b161f3111e6fded1c9857fa3a149 >> Description: >> >> This patch is to delay the enabling of interrupt till smp_finish . So >> that kthread_bind can safely bind threads to any possible cpu. Without >> this change interrupt should occur beofre the processor was >> completely up, and the softirq threads were unable to schedule on the >> processor and then ran on the wrong CPU. >> >> Signed-off-by: Sadasivan Shaiju >> --- >> arch/mips/cavium-octeon/smp.c | 3 ++- >> 1 files changed, 2 insertions(+), 1 deletions(-) >> >> diff --git a/arch/mips/cavium-octeon/smp.c >> b/arch/mips/cavium-octeon/smp.c index ff21542..c7de7ac 100644 >> --- a/arch/mips/cavium-octeon/smp.c >> +++ b/arch/mips/cavium-octeon/smp.c >> @@ -308,7 +308,6 @@ static void octeon_init_secondary(void) >> octeon_init_cvmcount(); >> >> octeon_irq_setup_secondary(); >> - raw_local_irq_enable(); >> } >> >> /** >> @@ -365,6 +364,8 @@ static void octeon_smp_finish(void) >> >> /* to generate the first CPU timer interrupt */ >> write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); >> + /* enable local interrupts */ >> + raw_local_irq_enable(); >> } >> >> /** >> -- 1.7.0.1