From: David Vrabel <david.vrabel@citrix.com>
To: Mukesh Rathor <mukesh.rathor@oracle.com>, <boris.ostrovsky@oracle.com>
Cc: <xen-devel@lists.xenproject.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [V0 PATCH 0/2] AMD PVH domU support
Date: Fri, 22 Aug 2014 14:52:41 +0100 [thread overview]
Message-ID: <53F74B29.4090601@citrix.com> (raw)
In-Reply-To: <1408587400-18663-1-git-send-email-mukesh.rathor@oracle.com>
On 21/08/14 03:16, Mukesh Rathor wrote:
> Hi,
>
> Here's first stab at AMD PVH domU support. Pretty much the only thing
> needed is EFER bits set. Please review.
I'm not going to accept this until there is some ABI documentation
stating explicitly what state non-boot CPUs will be in.
I'm particularly concerned that: a) there is a difference between AMD
and Intel; and b) you want to change the ABI by clearing a the EFER.SCE bit.
David
next prev parent reply other threads:[~2014-08-22 13:52 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-21 2:16 [V0 PATCH 0/2] AMD PVH domU support Mukesh Rathor
2014-08-21 2:16 ` [V0 PATCH 1/2] AMD-PVH: set EFER.NX and EFER.SCE for the boot vcpu Mukesh Rathor
2014-08-22 1:39 ` [Xen-devel] " Konrad Rzeszutek Wilk
2014-08-22 2:46 ` Mukesh Rathor
2014-08-22 3:32 ` Konrad Rzeszutek Wilk
2014-08-22 4:41 ` Borislav Petkov
2014-08-22 19:09 ` Mukesh Rathor
2014-08-22 23:29 ` Mukesh Rathor
2014-08-21 2:16 ` [V0 PATCH 2/2] AMD-PVH: set EFER.NX and EFER.SCE for secondary vcpus Mukesh Rathor
2014-08-22 13:52 ` David Vrabel [this message]
2014-08-22 13:55 ` [V0 PATCH 0/2] AMD PVH domU support David Vrabel
2014-08-22 19:15 ` Mukesh Rathor
2014-08-22 22:20 ` Mukesh Rathor
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