From: David Vrabel <david.vrabel@citrix.com>
To: Mukesh Rathor <mukesh.rathor@oracle.com>,
<boris.ostrovsky@oracle.com>, <david.vrabel@citrix.com>
Cc: <xen-devel@lists.xenproject.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [Xen-devel] [V1 PATCH 2/2] PVH: set EFER.NX and EFER.SCE for secondary vcpus
Date: Thu, 28 Aug 2014 15:24:46 +0100 [thread overview]
Message-ID: <53FF3BAE.5060807@citrix.com> (raw)
In-Reply-To: <1409178815-2026-3-git-send-email-mukesh.rathor@oracle.com>
On 27/08/14 23:33, Mukesh Rathor wrote:
> This patch addresses three things for a pvh secondary vcpu:
I don't understand why you have separated this into two patches. Please
fold into one.
> Please note: We create a new glue assembly entry point because the
> secondary vcpus come up on kernel page tables that have pte.NX
> bits set. While on Intel these are ignored if EFER.NX is not set, on
> AMD a RSVD bit fault is generated.
Please try and unify the early CPU init code for boot and secondary CPUs.
Native manages to do this (secondary_startup_64 is called for boot and
secondary CPUs).
> + /* Gather features to see if NX implemented. (no EFER.NX on intel) */
EFER.NXE does exist on Intel.
David
next prev parent reply other threads:[~2014-08-28 14:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-27 22:33 [V1 PATCH 0/2] Linux PVH: set EFER bits Mukesh Rathor
2014-08-27 22:33 ` [V1 PATCH 1/2] PVH: set EFER.NX and EFER.SCE for boot vcpu Mukesh Rathor
2014-08-28 14:18 ` [Xen-devel] " David Vrabel
2014-08-28 23:59 ` Mukesh Rathor
2014-08-27 22:33 ` [V1 PATCH 2/2] PVH: set EFER.NX and EFER.SCE for secondary vcpus Mukesh Rathor
2014-08-28 14:24 ` David Vrabel [this message]
2014-08-28 14:08 ` [Xen-devel] [V1 PATCH 0/2] Linux PVH: set EFER bits David Vrabel
2014-08-28 14:15 ` Jan Beulich
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