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Message-ID: <54071C7B.4090805@linaro.org>
Date: Wed, 03 Sep 2014 15:49:47 +0200
From: Daniel Lezcano <daniel.lezcano@linaro.org>
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To: Soren Brinkmann <soren.brinkmann@xilinx.com>,
        Michal Simek <michal.simek@xilinx.com>
CC: Russell King <linux@arm.linux.org.uk>,
        "Rafael J. Wysocki" <rjw@rjwysocki.net>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
        Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
        Pawel Moll <pawel.moll@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Kumar Gala <galak@codeaurora.org>
Subject: Re: [PATCH v2 3/9] ARM: zynq: DT: Add DDRC node
References: <1409692754-13437-1-git-send-email-soren.brinkmann@xilinx.com> <1409692754-13437-4-git-send-email-soren.brinkmann@xilinx.com>
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On 09/02/2014 11:19 PM, Soren Brinkmann wrote:
> Add the DDR controller to the Zynq devicetree.
>
> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

> ---
>   arch/arm/boot/dts/zynq-7000.dtsi | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> index 6cc83d4c6c76..587cadcf7001 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -146,6 +146,11 @@
>   			cache-level = <2>;
>   		};
>
> +		memory-controller@f8006000 {
> +			compatible = "xlnx,zynq-ddrc-a05";
> +			reg = <0xf8006000 0x1000>;
> +		} ;
> +
>   		uart0: serial@e0000000 {
>   			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
>   			status = "disabled";
>


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