[PATCH 0/2] irqchip: Broadcom BCM7120-style Level 2 interrupt controller

[PATCH 0/2] irqchip: Broadcom BCM7120-style Level 2 interrupt controller

[Florian Fainelli]

Hi Jason, Thomas,

This patch set adds support for the second type of Level-2 interrupt controller
found on Broadcom Set Top Box hardware.

Thanks!

Florian Fainelli (2):
  irqchip: add Broadcom BCM7120-style Level 2 interrupt controller
  Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

 .../interrupt-controller/brcm,bcm7120-l2-intc.txt  |  44 ++++
 drivers/irqchip/Makefile                           |   3 +-
 drivers/irqchip/irq-bcm7120-l2.c                   | 222 +++++++++++++++++++++
 3 files changed, 268 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
 create mode 100644 drivers/irqchip/irq-bcm7120-l2.c

-- 
1.9.1

[PATCH 1/2] irqchip: add Broadcom BCM7120-style Level 2 interrupt controller

[Florian Fainelli]

This patch adds support for the Level-2 interrupt controller
hardware found in Broadcom Set Top Box System-on-a-Chip devices. This
interrupt controller is implemented using a single enable register.

This interrupt controller is always present on the platforms supported
by the irq-brcmstb-l2 driver, hence the reason why both are compiled
using the same Kconfig symbol.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/irqchip/Makefile         |   3 +-
 drivers/irqchip/irq-bcm7120-l2.c | 222 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 224 insertions(+), 1 deletion(-)
 create mode 100644 drivers/irqchip/irq-bcm7120-l2.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 73052ba9ca62..824f5eb780b6 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -33,4 +33,5 @@ obj-$(CONFIG_TB10X_IRQC)		+= irq-tb10x.o
 obj-$(CONFIG_XTENSA)			+= irq-xtensa-pic.o
 obj-$(CONFIG_XTENSA_MX)			+= irq-xtensa-mx.o
 obj-$(CONFIG_IRQ_CROSSBAR)		+= irq-crossbar.o
-obj-$(CONFIG_BRCMSTB_L2_IRQ)		+= irq-brcmstb-l2.o
+obj-$(CONFIG_BRCMSTB_L2_IRQ)		+= irq-brcmstb-l2.o \
+					   irq-bcm7120-l2.o
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c
new file mode 100644
index 000000000000..1bba8978a622
--- /dev/null
+++ b/drivers/irqchip/irq-bcm7120-l2.c
@@ -0,0 +1,222 @@
+/*
+ * Broadcom BCM7120 style Level 2 interrupt controller driver
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/reboot.h>
+#include <linux/irqchip/chained_irq.h>
+
+#include "irqchip.h"
+
+#include <asm/mach/irq.h>
+
+/* Register offset in the L2 interrupt controller */
+#define IRQEN		0x00
+#define IRQSTAT		0x04
+
+struct bcm7120_l2_intc_data {
+	void __iomem *base;
+	struct irq_domain *domain;
+	bool can_wake;
+	u32 irq_fwd_mask;
+	u32 irq_map_mask;
+	u32 saved_mask;
+};
+
+static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
+{
+	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct irq_chip_generic *gc = irq_get_domain_generic_chip(b->domain, 0);
+	u32 status;
+
+	chained_irq_enter(chip, desc);
+
+	irq_gc_lock(gc);
+	status = __raw_readl(b->base + IRQSTAT);
+	irq_gc_unlock(gc);
+
+	if (status == 0) {
+		do_bad_IRQ(irq, desc);
+		goto out;
+	}
+
+	do {
+		irq = ffs(status) - 1;
+		status &= ~(1 << irq);
+		generic_handle_irq(irq_find_mapping(b->domain, irq));
+	} while (status);
+
+out:
+	chained_irq_exit(chip, desc);
+}
+
+static void bcm7120_l2_intc_suspend(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct bcm7120_l2_intc_data *b = gc->private;
+	u32 reg;
+
+	irq_gc_lock(gc);
+	/* Save the current mask and the interrupt forward mask */
+	b->saved_mask = __raw_readl(b->base) | b->irq_fwd_mask;
+	if (b->can_wake) {
+		reg = b->saved_mask | gc->wake_active;
+		__raw_writel(reg, b->base);
+	}
+	irq_gc_unlock(gc);
+}
+
+static void bcm7120_l2_intc_resume(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct bcm7120_l2_intc_data *b = gc->private;
+
+	/* Restore the saved mask */
+	irq_gc_lock(gc);
+	__raw_writel(b->saved_mask, b->base);
+	irq_gc_unlock(gc);
+}
+
+static int bcm7120_l2_intc_init_one(struct device_node *dn,
+					struct bcm7120_l2_intc_data *data,
+					int irq, const __be32 *map_mask)
+{
+	int parent_irq;
+
+	parent_irq = irq_of_parse_and_map(dn, irq);
+	if (parent_irq < 0) {
+		pr_err("failed to map interrupt %d\n", irq);
+		return parent_irq;
+	}
+
+	data->irq_map_mask |= be32_to_cpup(map_mask + irq);
+
+	irq_set_handler_data(parent_irq, data);
+	irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);
+
+	return 0;
+}
+
+int __init bcm7120_l2_intc_of_init(struct device_node *dn,
+					struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	struct bcm7120_l2_intc_data *data;
+	struct irq_chip_generic *gc;
+	struct irq_chip_type *ct;
+	const __be32 *map_mask;
+	int num_parent_irqs;
+	int ret = 0, len, irq;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->base = of_iomap(dn, 0);
+	if (!data->base) {
+		pr_err("failed to remap intc L2 registers\n");
+		ret = -ENOMEM;
+		goto out_free;
+	}
+
+	if (of_property_read_u32(dn, "brcm,int-fwd-mask", &data->irq_fwd_mask))
+		data->irq_fwd_mask = 0;
+
+	/* Enable all interrupt specified in the interrupt forward mask and have
+	 * the other disabled
+	 */
+	__raw_writel(data->irq_fwd_mask, data->base + IRQEN);
+
+	num_parent_irqs = of_irq_count(dn);
+	if (num_parent_irqs <= 0) {
+		pr_err("invalid number of parent interrupts\n");
+		ret = -ENOMEM;
+		goto out_unmap;
+	}
+
+	map_mask = of_get_property(dn, "brcm,int-map-mask", &len);
+	if (!map_mask || (len != (sizeof(*map_mask) * num_parent_irqs))) {
+		pr_err("invalid brcm,int-map-mask property\n");
+		ret = -EINVAL;
+		goto out_unmap;
+	}
+
+	for (irq = 0; irq < num_parent_irqs; irq++) {
+		ret = bcm7120_l2_intc_init_one(dn, data, irq, map_mask);
+		if (ret)
+			continue;
+	}
+
+	data->domain = irq_domain_add_linear(dn, 32,
+					&irq_generic_chip_ops, NULL);
+	if (!data->domain) {
+		ret = -ENOMEM;
+		goto out_unmap;
+	}
+
+	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
+				dn->full_name, handle_level_irq, clr, 0,
+				IRQ_GC_INIT_MASK_CACHE);
+	if (ret) {
+		pr_err("failed to allocate generic irq chip\n");
+		goto out_free_domain;
+	}
+
+	gc = irq_get_domain_generic_chip(data->domain, 0);
+	gc->unused = 0xfffffff & ~data->irq_map_mask;
+	gc->reg_base = data->base;
+	gc->private = data;
+	ct = gc->chip_types;
+
+	ct->regs.mask = IRQEN;
+	ct->chip.irq_mask = irq_gc_mask_clr_bit;
+	ct->chip.irq_unmask = irq_gc_mask_set_bit;
+	ct->chip.irq_ack = irq_gc_noop;
+	ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
+	ct->chip.irq_resume = bcm7120_l2_intc_resume;
+
+	if (of_property_read_bool(dn, "brcm,irq-can-wake")) {
+		data->can_wake = true;
+		/* This IRQ chip can wake the system, set all relevant child
+		 * interupts in wake_enabled mask
+		 */
+		gc->wake_enabled = 0xffffffff;
+		gc->wake_enabled &= ~gc->unused;
+		ct->chip.irq_set_wake = irq_gc_set_wake;
+	}
+
+	pr_info("registered BCM7120 L2 intc (mem: 0x%p, parent IRQ(s): %d)\n",
+			data->base, num_parent_irqs);
+
+	return 0;
+
+out_free_domain:
+	irq_domain_remove(data->domain);
+out_unmap:
+	iounmap(data->base);
+out_free:
+	kfree(data);
+	return ret;
+}
+IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,bcm7120-l2-intc",
+		bcm7120_l2_intc_of_init);
-- 
1.9.1

Re: [PATCH 1/2] irqchip: add Broadcom BCM7120-style Level 2 interrupt controller

[Thomas Gleixner]

On Thu, 28 Aug 2014, Florian Fainelli wrote:
> +static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
> +{
> +	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	struct irq_chip_generic *gc = irq_get_domain_generic_chip(b->domain, 0);
> +	u32 status;
> +
> +	chained_irq_enter(chip, desc);
> +
> +	irq_gc_lock(gc);
> +	status = __raw_readl(b->base + IRQSTAT);
> +	irq_gc_unlock(gc);

Why do you need locking around the status read out?

> +	for (irq = 0; irq < num_parent_irqs; irq++) {
> +		ret = bcm7120_l2_intc_init_one(dn, data, irq, map_mask);
> +		if (ret)
> +			continue;

What's the exact purpose of this "if (ret)" construct?

Thanks,

	tglx

Re: [PATCH 1/2] irqchip: add Broadcom BCM7120-style Level 2 interrupt controller

[Florian Fainelli]

On 09/03/2014 05:18 AM, Thomas Gleixner wrote:
> On Thu, 28 Aug 2014, Florian Fainelli wrote:
>> +static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
>> +{
>> +	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
>> +	struct irq_chip *chip = irq_desc_get_chip(desc);
>> +	struct irq_chip_generic *gc = irq_get_domain_generic_chip(b->domain, 0);
>> +	u32 status;
>> +
>> +	chained_irq_enter(chip, desc);
>> +
>> +	irq_gc_lock(gc);
>> +	status = __raw_readl(b->base + IRQSTAT);
>> +	irq_gc_unlock(gc);
> 
> Why do you need locking around the status read out?

I was worried about potential concurrency issues, but I suppose that
this is just extra carefulness that brings nothing.

> 
>> +	for (irq = 0; irq < num_parent_irqs; irq++) {
>> +		ret = bcm7120_l2_intc_init_one(dn, data, irq, map_mask);
>> +		if (ret)
>> +			continue;
> 
> What's the exact purpose of this "if (ret)" construct?

It's pretty much useless the way it is now, I will rework that.

Thanks for the review!
--
Florian

[PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Florian Fainelli]

This patch adds the Device Tree binding document for the Broadcom
BCM7120-style Set-top-box Level 2 interrupt controller hardware.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 .../interrupt-controller/brcm,bcm7120-l2-intc.txt  | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
new file mode 100644
index 000000000000..3818ffed7347
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
@@ -0,0 +1,44 @@
+Broadcom BCM7120-style Level 2 interrupt controller
+
+Required properties:
+
+- compatible: should be "brcm,bcm7120-l2-intc"
+- reg: specifies the base physical address and size of the registers
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+  source, should be 1.
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+  this one is cascaded from
+- interrupts: specifies the interrupt line(s) in the interrupt-parent domain
+  to be used for cascading
+- brcm,int-map-mask: 32-bits bit mask describing how the interrupts at this level
+  map to their respective parents. Should match exactly the number of interrupts
+  specified in the 'interrupts' property.
+
+Optional properties:
+
+- interrupt-names: if present, the litteral names for the parent interrupts
+  specified in the 'interrupts' property.
+
+- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
+  wakeup source for system suspend/resume.
+
+- brcm,int-fwd-mask: if present, a 32-bits bit mask describing the interrupts
+  which need to be enabled in this controller to flow to the higher level
+  interrupt controller. This is typically needed for the UARTs interrupts to
+  flow through the top-level interrupt controller (e.g: ARM GIC on ARM-based
+  platforms).
+
+Example:
+
+irq0_intc: interrupt-controller@f0406800 {
+	compatible = "brcm,bcm7120-l2-intc";
+	interrupt-parent = <&intc>;
+	#interrupt-cells = <1>;
+	reg = <0xf0406800 0x8>;
+	interrupt-controller;
+	interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+	interrupt-names = "upg_main", "upg_bsc";
+	brcm,int-map-mask = <0xeb8>, <0x140>;
+	brcm,int-fwd-mask = <0x7>;
+};
-- 
1.9.1

Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Thomas Gleixner]

You forgot to CC the device tree dudes. We want an ack on the bindings
before they materialize in Linus tree.

Thanks,

	tglx

On Thu, 28 Aug 2014, Florian Fainelli wrote:

> This patch adds the Device Tree binding document for the Broadcom
> BCM7120-style Set-top-box Level 2 interrupt controller hardware.
> 
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  .../interrupt-controller/brcm,bcm7120-l2-intc.txt  | 44 ++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> new file mode 100644
> index 000000000000..3818ffed7347
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> @@ -0,0 +1,44 @@
> +Broadcom BCM7120-style Level 2 interrupt controller
> +
> +Required properties:
> +
> +- compatible: should be "brcm,bcm7120-l2-intc"
> +- reg: specifies the base physical address and size of the registers
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: specifies the number of cells needed to encode an interrupt
> +  source, should be 1.
> +- interrupt-parent: specifies the phandle to the parent interrupt controller
> +  this one is cascaded from
> +- interrupts: specifies the interrupt line(s) in the interrupt-parent domain
> +  to be used for cascading
> +- brcm,int-map-mask: 32-bits bit mask describing how the interrupts at this level
> +  map to their respective parents. Should match exactly the number of interrupts
> +  specified in the 'interrupts' property.
> +
> +Optional properties:
> +
> +- interrupt-names: if present, the litteral names for the parent interrupts
> +  specified in the 'interrupts' property.
> +
> +- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
> +  wakeup source for system suspend/resume.
> +
> +- brcm,int-fwd-mask: if present, a 32-bits bit mask describing the interrupts
> +  which need to be enabled in this controller to flow to the higher level
> +  interrupt controller. This is typically needed for the UARTs interrupts to
> +  flow through the top-level interrupt controller (e.g: ARM GIC on ARM-based
> +  platforms).
> +
> +Example:
> +
> +irq0_intc: interrupt-controller@f0406800 {
> +	compatible = "brcm,bcm7120-l2-intc";
> +	interrupt-parent = <&intc>;
> +	#interrupt-cells = <1>;
> +	reg = <0xf0406800 0x8>;
> +	interrupt-controller;
> +	interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
> +	interrupt-names = "upg_main", "upg_bsc";
> +	brcm,int-map-mask = <0xeb8>, <0x140>;
> +	brcm,int-fwd-mask = <0x7>;
> +};
> -- 
> 1.9.1
> 
> 

Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Mark Rutland]

On Wed, Sep 03, 2014 at 01:13:02PM +0100, Thomas Gleixner wrote:
> You forgot to CC the device tree dudes. We want an ack on the bindings
> before they materialize in Linus tree.

Thanks for the Cc.

Florian, in future could you please Cc for both the binding and driver?
So long as it's obvious which patch introduces the binding other can
choose to ignore the driver, but for me it's useful context.

> 
> Thanks,
> 
> 	tglx
> 
> On Thu, 28 Aug 2014, Florian Fainelli wrote:
> 
> > This patch adds the Device Tree binding document for the Broadcom
> > BCM7120-style Set-top-box Level 2 interrupt controller hardware.
> > 
> > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> > ---
> >  .../interrupt-controller/brcm,bcm7120-l2-intc.txt  | 44 ++++++++++++++++++++++
> >  1 file changed, 44 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> > new file mode 100644
> > index 000000000000..3818ffed7347
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> > @@ -0,0 +1,44 @@
> > +Broadcom BCM7120-style Level 2 interrupt controller
> > +
> > +Required properties:
> > +
> > +- compatible: should be "brcm,bcm7120-l2-intc"

Is this a custom block for the bcm7120?

Does the IP block not have a more specific name?

> > +- reg: specifies the base physical address and size of the registers
> > +- interrupt-controller: identifies the node as an interrupt controller
> > +- #interrupt-cells: specifies the number of cells needed to encode an interrupt
> > +  source, should be 1.

... and valid values are?

> > +- interrupt-parent: specifies the phandle to the parent interrupt controller
> > +  this one is cascaded from
> > +- interrupts: specifies the interrupt line(s) in the interrupt-parent domain
> > +  to be used for cascading

The domain is a software construct, so I don't think it needs to be
mentuioned in the binding doc. All that this proeprty describes is the
lines.

> > +- brcm,int-map-mask: 32-bits bit mask describing how the interrupts
> > at this level
> > +  map to their respective parents. Should match exactly the number of interrupts
> > +  specified in the 'interrupts' property.

I don't follow.

Surely this should be static, and we know the 1-1 mapping, or this is
dynamic and should be SW-configured?

> > +Optional properties:
> > +
> > +- interrupt-names: if present, the litteral names for the parent interrupts
> > +  specified in the 'interrupts' property.

If you use the interrupt-names property, it should contain the names of
the interrupts from the POV of this device. Those names must be
specified in the binding doc.

This is useless as-is.

> > +- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
> > +  wakeup source for system suspend/resume.

How variable is this?

I realise have properties like this elsewhere, but it seems to be
hacking around the lack of a decent power domain interface for figuring
this out.

> > +- brcm,int-fwd-mask: if present, a 32-bits bit mask describing the interrupts
> > +  which need to be enabled in this controller to flow to the higher level
> > +  interrupt controller. This is typically needed for the UARTs interrupts to
> > +  flow through the top-level interrupt controller (e.g: ARM GIC on ARM-based
> > +  platforms).
> > +

I don't follow why this property is needed at all. Is this a mechanism
to bypass this controller entirely? Why should this be described as a
fixed HW property?

Thanks,
Mark.

> > +Example:
> > +
> > +irq0_intc: interrupt-controller@f0406800 {
> > +	compatible = "brcm,bcm7120-l2-intc";
> > +	interrupt-parent = <&intc>;
> > +	#interrupt-cells = <1>;
> > +	reg = <0xf0406800 0x8>;
> > +	interrupt-controller;
> > +	interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
> > +	interrupt-names = "upg_main", "upg_bsc";
> > +	brcm,int-map-mask = <0xeb8>, <0x140>;
> > +	brcm,int-fwd-mask = <0x7>;
> > +};
> > -- 
> > 1.9.1
> > 
> > 
> --
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Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Florian Fainelli]

On 09/03/2014 05:43 AM, Mark Rutland wrote:
> On Wed, Sep 03, 2014 at 01:13:02PM +0100, Thomas Gleixner wrote:
>> You forgot to CC the device tree dudes. We want an ack on the bindings
>> before they materialize in Linus tree.
> 
> Thanks for the Cc.
> 
> Florian, in future could you please Cc for both the binding and driver?
> So long as it's obvious which patch introduces the binding other can
> choose to ignore the driver, but for me it's useful context.
> 
>>
>> Thanks,
>>
>> 	tglx
>>
>> On Thu, 28 Aug 2014, Florian Fainelli wrote:
>>
>>> This patch adds the Device Tree binding document for the Broadcom
>>> BCM7120-style Set-top-box Level 2 interrupt controller hardware.
>>>
>>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>>> ---
>>>  .../interrupt-controller/brcm,bcm7120-l2-intc.txt  | 44 ++++++++++++++++++++++
>>>  1 file changed, 44 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
>>> new file mode 100644
>>> index 000000000000..3818ffed7347
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
>>> @@ -0,0 +1,44 @@
>>> +Broadcom BCM7120-style Level 2 interrupt controller
>>> +
>>> +Required properties:
>>> +
>>> +- compatible: should be "brcm,bcm7120-l2-intc"
> 
> Is this a custom block for the bcm7120?

This is a custom block that started being used with bcm7120 and that we
inherited, unmodified, in newer BCM7xxx designs since then, hence the
name we picked up.

> 
> Does the IP block not have a more specific name?

I wish there was one, I had to dig through the verilog sources to find
which chip this interrupt controller first started to appear, and the
filename was not too helpful either.

> 
>>> +- reg: specifies the base physical address and size of the registers
>>> +- interrupt-controller: identifies the node as an interrupt controller
>>> +- #interrupt-cells: specifies the number of cells needed to encode an interrupt
>>> +  source, should be 1.
> 
> ... and valid values are?

0 to 31, this is the interrupt number, will fix that.

> 
>>> +- interrupt-parent: specifies the phandle to the parent interrupt controller
>>> +  this one is cascaded from
>>> +- interrupts: specifies the interrupt line(s) in the interrupt-parent domain
>>> +  to be used for cascading
> 
> The domain is a software construct, so I don't think it needs to be
> mentuioned in the binding doc. All that this proeprty describes is the
> lines.

Will fix that.

> 
>>> +- brcm,int-map-mask: 32-bits bit mask describing how the interrupts
>>> at this level
>>> +  map to their respective parents. Should match exactly the number of interrupts
>>> +  specified in the 'interrupts' property.
> 
> I don't follow.
> 
> Surely this should be static, and we know the 1-1 mapping, or this is
> dynamic and should be SW-configured?

This is static for a given instance of this interrupt controller on a
particular brcmstb chip. BCM7445 will have something different here than
e.g: BCM7366 or BCM7439 which are also from the same family.

Not all 32 bits within this interrupt controller will map to wired
interrupts, so the point of this bitmask is to:

- tell how many valid interrupt sources there are
- tell how a given bitmask maps to its corresponding L1 interrupt line
number

So this is not much to know the 1:1, but to know the the 1:many mapping,
the example might make it a little clearer how this works

> 
>>> +Optional properties:
>>> +
>>> +- interrupt-names: if present, the litteral names for the parent interrupts
>>> +  specified in the 'interrupts' property.
> 
> If you use the interrupt-names property, it should contain the names of
> the interrupts from the POV of this device. Those names must be
> specified in the binding doc.

Since this also varies on a per-chip basis, I can certainly add each
valid names for each chips out there, but that does not sound useful,
maybe let's just drop that property, we don't use it anyway since we
perform lookups by indexes, and that is safe to do.

> 
> This is useless as-is.
> 
>>> +- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
>>> +  wakeup source for system suspend/resume.
> 
> How variable is this?

There's two instances of this interrupt controller on most SoCs, one
that can wake up the system, one that cannot, see below.

> 
> I realise have properties like this elsewhere, but it seems to be
> hacking around the lack of a decent power domain interface for figuring
> this out.

Humm, I kind of see your point here with the power domains, I don't see
a big problem with specifying that property though, at most this becomes
redundant when we have a power domain representation (which will be very
simple: always-on and everything else).

> 
>>> +- brcm,int-fwd-mask: if present, a 32-bits bit mask describing the interrupts
>>> +  which need to be enabled in this controller to flow to the higher level
>>> +  interrupt controller. This is typically needed for the UARTs interrupts to
>>> +  flow through the top-level interrupt controller (e.g: ARM GIC on ARM-based
>>> +  platforms).
>>> +
> 
> I don't follow why this property is needed at all. Is this a mechanism
> to bypass this controller entirely? Why should this be described as a
> fixed HW property?

This interrupt controller has traditionally (not necessarily for good
reasons) been the placeholder for special bits that control whether our
UARTs level 1 interrupts (wired to the ARM GIC) will flow to the L1
interrupt.

We discussed initially with Arnd Bergman about how to best approach
this, and he was happy with a bitmask since:

a) that is a one-time initialization thing that can happen anywhere in
the kernel before UART interrupts get used (so before user-space gets
scheduled)

b) we need to save/restore that bitmask during suspend/resume

c) this is not a real interrupt bit, we need to set this bit, but we
will not get any interrupt at this particular interrupt controller level
for UARTs, so this is totally transparent for the UART driver

Once again, the bitmask values varies on a per-chip basis, though the
fundamentals are the same.

> 
> Thanks,
> Mark.
> 
>>> +Example:
>>> +
>>> +irq0_intc: interrupt-controller@f0406800 {
>>> +	compatible = "brcm,bcm7120-l2-intc";
>>> +	interrupt-parent = <&intc>;
>>> +	#interrupt-cells = <1>;
>>> +	reg = <0xf0406800 0x8>;
>>> +	interrupt-controller;
>>> +	interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
>>> +	interrupt-names = "upg_main", "upg_bsc";
>>> +	brcm,int-map-mask = <0xeb8>, <0x140>;
>>> +	brcm,int-fwd-mask = <0x7>;
>>> +};
>>> -- 
>>> 1.9.1
>>>
>>>
>> --
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Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Mark Rutland]

On Wed, Sep 03, 2014 at 05:59:58PM +0100, Florian Fainelli wrote:
> On 09/03/2014 05:43 AM, Mark Rutland wrote:
> > On Wed, Sep 03, 2014 at 01:13:02PM +0100, Thomas Gleixner wrote:
> >> You forgot to CC the device tree dudes. We want an ack on the bindings
> >> before they materialize in Linus tree.
> > 
> > Thanks for the Cc.
> > 
> > Florian, in future could you please Cc for both the binding and driver?
> > So long as it's obvious which patch introduces the binding other can
> > choose to ignore the driver, but for me it's useful context.
> > 
> >>
> >> Thanks,
> >>
> >> 	tglx
> >>
> >> On Thu, 28 Aug 2014, Florian Fainelli wrote:
> >>
> >>> This patch adds the Device Tree binding document for the Broadcom
> >>> BCM7120-style Set-top-box Level 2 interrupt controller hardware.
> >>>
> >>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> >>> ---
> >>>  .../interrupt-controller/brcm,bcm7120-l2-intc.txt  | 44 ++++++++++++++++++++++
> >>>  1 file changed, 44 insertions(+)
> >>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> >>> new file mode 100644
> >>> index 000000000000..3818ffed7347
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> >>> @@ -0,0 +1,44 @@
> >>> +Broadcom BCM7120-style Level 2 interrupt controller
> >>> +
> >>> +Required properties:
> >>> +
> >>> +- compatible: should be "brcm,bcm7120-l2-intc"
> > 
> > Is this a custom block for the bcm7120?
> 
> This is a custom block that started being used with bcm7120 and that we
> inherited, unmodified, in newer BCM7xxx designs since then, hence the
> name we picked up.

Ok.

> > 
> > Does the IP block not have a more specific name?
> 
> I wish there was one, I had to dig through the verilog sources to find
> which chip this interrupt controller first started to appear, and the
> filename was not too helpful either.

Fair enough.

[...]

> >>> +- brcm,int-map-mask: 32-bits bit mask describing how the interrupts
> >>> at this level
> >>> +  map to their respective parents. Should match exactly the number of interrupts
> >>> +  specified in the 'interrupts' property.
> > 
> > I don't follow.
> > 
> > Surely this should be static, and we know the 1-1 mapping, or this is
> > dynamic and should be SW-configured?
> 
> This is static for a given instance of this interrupt controller on a
> particular brcmstb chip. BCM7445 will have something different here than
> e.g: BCM7366 or BCM7439 which are also from the same family.
> 
> Not all 32 bits within this interrupt controller will map to wired
> interrupts, so the point of this bitmask is to:
> 
> - tell how many valid interrupt sources there are
> - tell how a given bitmask maps to its corresponding L1 interrupt line
> number
> 
> So this is not much to know the 1:1, but to know the the 1:many mapping,
> the example might make it a little clearer how this works

I'll have to give the example another scan, it's not immediately clear
how the latter portion works.

> >>> +Optional properties:
> >>> +
> >>> +- interrupt-names: if present, the litteral names for the parent interrupts
> >>> +  specified in the 'interrupts' property.
> > 
> > If you use the interrupt-names property, it should contain the names of
> > the interrupts from the POV of this device. Those names must be
> > specified in the binding doc.
> 
> Since this also varies on a per-chip basis, I can certainly add each
> valid names for each chips out there, but that does not sound useful,
> maybe let's just drop that property, we don't use it anyway since we
> perform lookups by indexes, and that is safe to do.

Ok. It sounds like the index would be the thing to use here.

> >>> +- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
> >>> +  wakeup source for system suspend/resume.
> > 
> > How variable is this?
> 
> There's two instances of this interrupt controller on most SoCs, one
> that can wake up the system, one that cannot, see below.
> 
> > 
> > I realise have properties like this elsewhere, but it seems to be
> > hacking around the lack of a decent power domain interface for figuring
> > this out.
> 
> Humm, I kind of see your point here with the power domains, I don't see
> a big problem with specifying that property though, at most this becomes
> redundant when we have a power domain representation (which will be very
> simple: always-on and everything else).

Sure, we seem to have done that elsewhere.

> >>> +- brcm,int-fwd-mask: if present, a 32-bits bit mask describing the interrupts
> >>> +  which need to be enabled in this controller to flow to the higher level
> >>> +  interrupt controller. This is typically needed for the UARTs interrupts to
> >>> +  flow through the top-level interrupt controller (e.g: ARM GIC on ARM-based
> >>> +  platforms).
> >>> +
> > 
> > I don't follow why this property is needed at all. Is this a mechanism
> > to bypass this controller entirely? Why should this be described as a
> > fixed HW property?
> 
> This interrupt controller has traditionally (not necessarily for good
> reasons) been the placeholder for special bits that control whether our
> UARTs level 1 interrupts (wired to the ARM GIC) will flow to the L1
> interrupt.

So basically setting these bits unmasks some irq lines inpout to the
GIC?

> We discussed initially with Arnd Bergman about how to best approach
> this, and he was happy with a bitmask since:
> 
> a) that is a one-time initialization thing that can happen anywhere in
> the kernel before UART interrupts get used (so before user-space gets
> scheduled)

That feels a little dodgy to me, but perhaps that's ok.

> 
> b) we need to save/restore that bitmask during suspend/resume
> 
> c) this is not a real interrupt bit, we need to set this bit, but we
> will not get any interrupt at this particular interrupt controller level
> for UARTs, so this is totally transparent for the UART driver
> 
> Once again, the bitmask values varies on a per-chip basis, though the
> fundamentals are the same.

Thanks for the explanation.

Mark.

Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Florian Fainelli]

On 09/05/2014 02:05 AM, Mark Rutland wrote:
> On Wed, Sep 03, 2014 at 05:59:58PM +0100, Florian Fainelli wrote:
>> On 09/03/2014 05:43 AM, Mark Rutland wrote:
>>> On Wed, Sep 03, 2014 at 01:13:02PM +0100, Thomas Gleixner wrote:
>>>> You forgot to CC the device tree dudes. We want an ack on the bindings
>>>> before they materialize in Linus tree.
>>>
>>> Thanks for the Cc.
>>>
>>> Florian, in future could you please Cc for both the binding and driver?
>>> So long as it's obvious which patch introduces the binding other can
>>> choose to ignore the driver, but for me it's useful context.
>>>
>>>>
>>>> Thanks,
>>>>
>>>> 	tglx
>>>>
>>>> On Thu, 28 Aug 2014, Florian Fainelli wrote:
>>>>
>>>>> This patch adds the Device Tree binding document for the Broadcom
>>>>> BCM7120-style Set-top-box Level 2 interrupt controller hardware.
>>>>>
>>>>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>>>>> ---
>>>>>  .../interrupt-controller/brcm,bcm7120-l2-intc.txt  | 44 ++++++++++++++++++++++
>>>>>  1 file changed, 44 insertions(+)
>>>>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
>>>>> new file mode 100644
>>>>> index 000000000000..3818ffed7347
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
>>>>> @@ -0,0 +1,44 @@
>>>>> +Broadcom BCM7120-style Level 2 interrupt controller
>>>>> +
>>>>> +Required properties:
>>>>> +
>>>>> +- compatible: should be "brcm,bcm7120-l2-intc"
>>>
>>> Is this a custom block for the bcm7120?
>>
>> This is a custom block that started being used with bcm7120 and that we
>> inherited, unmodified, in newer BCM7xxx designs since then, hence the
>> name we picked up.
> 
> Ok.
> 
>>>
>>> Does the IP block not have a more specific name?
>>
>> I wish there was one, I had to dig through the verilog sources to find
>> which chip this interrupt controller first started to appear, and the
>> filename was not too helpful either.
> 
> Fair enough.
> 
> [...]
> 
>>>>> +- brcm,int-map-mask: 32-bits bit mask describing how the interrupts
>>>>> at this level
>>>>> +  map to their respective parents. Should match exactly the number of interrupts
>>>>> +  specified in the 'interrupts' property.
>>>
>>> I don't follow.
>>>
>>> Surely this should be static, and we know the 1-1 mapping, or this is
>>> dynamic and should be SW-configured?
>>
>> This is static for a given instance of this interrupt controller on a
>> particular brcmstb chip. BCM7445 will have something different here than
>> e.g: BCM7366 or BCM7439 which are also from the same family.
>>
>> Not all 32 bits within this interrupt controller will map to wired
>> interrupts, so the point of this bitmask is to:
>>
>> - tell how many valid interrupt sources there are
>> - tell how a given bitmask maps to its corresponding L1 interrupt line
>> number
>>
>> So this is not much to know the 1:1, but to know the the 1:many mapping,
>> the example might make it a little clearer how this works
> 
> I'll have to give the example another scan, it's not immediately clear
> how the latter portion works.

Had I CC'd you correctly in the first place you could see how that is
used, my bad.

This bitmask gets bitwise OR'd to set the unused bits in gc->unused, to
make sure there was no loss of information, I wanted to have one mask
per interrupt outputs, even though the code does combine that into a
single 32-bits wide mask.

> 
>>>>> +Optional properties:
>>>>> +
>>>>> +- interrupt-names: if present, the litteral names for the parent interrupts
>>>>> +  specified in the 'interrupts' property.
>>>
>>> If you use the interrupt-names property, it should contain the names of
>>> the interrupts from the POV of this device. Those names must be
>>> specified in the binding doc.
>>
>> Since this also varies on a per-chip basis, I can certainly add each
>> valid names for each chips out there, but that does not sound useful,
>> maybe let's just drop that property, we don't use it anyway since we
>> perform lookups by indexes, and that is safe to do.
> 
> Ok. It sounds like the index would be the thing to use here.
> 
>>>>> +- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
>>>>> +  wakeup source for system suspend/resume.
>>>
>>> How variable is this?
>>
>> There's two instances of this interrupt controller on most SoCs, one
>> that can wake up the system, one that cannot, see below.
>>
>>>
>>> I realise have properties like this elsewhere, but it seems to be
>>> hacking around the lack of a decent power domain interface for figuring
>>> this out.
>>
>> Humm, I kind of see your point here with the power domains, I don't see
>> a big problem with specifying that property though, at most this becomes
>> redundant when we have a power domain representation (which will be very
>> simple: always-on and everything else).
> 
> Sure, we seem to have done that elsewhere.
> 
>>>>> +- brcm,int-fwd-mask: if present, a 32-bits bit mask describing the interrupts
>>>>> +  which need to be enabled in this controller to flow to the higher level
>>>>> +  interrupt controller. This is typically needed for the UARTs interrupts to
>>>>> +  flow through the top-level interrupt controller (e.g: ARM GIC on ARM-based
>>>>> +  platforms).
>>>>> +
>>>
>>> I don't follow why this property is needed at all. Is this a mechanism
>>> to bypass this controller entirely? Why should this be described as a
>>> fixed HW property?
>>
>> This interrupt controller has traditionally (not necessarily for good
>> reasons) been the placeholder for special bits that control whether our
>> UARTs level 1 interrupts (wired to the ARM GIC) will flow to the L1
>> interrupt.
> 
> So basically setting these bits unmasks some irq lines inpout to the
> GIC?

Right, this is what happens. We prefer to use the GIC interrupts because
that provides more flexibility.

> 
>> We discussed initially with Arnd Bergman about how to best approach
>> this, and he was happy with a bitmask since:
>>
>> a) that is a one-time initialization thing that can happen anywhere in
>> the kernel before UART interrupts get used (so before user-space gets
>> scheduled)
> 
> That feels a little dodgy to me, but perhaps that's ok.

The other approach was to use the "interrupt-extended" property for the
UART nodes and have them reference both their GIC interrupt, and the
BCM7120-L2 interrupt, but that also requires UART driver/platform
modifications to account for that extra "interrupt", on which we are
only ever going to call enable_irq() and nothing more.

So, in the end, this turned out to be simpler to just read the
"brcm,irq-fwd-mask" property and apply it to the relevant register.

> 
>>
>> b) we need to save/restore that bitmask during suspend/resume
>>
>> c) this is not a real interrupt bit, we need to set this bit, but we
>> will not get any interrupt at this particular interrupt controller level
>> for UARTs, so this is totally transparent for the UART driver
>>
>> Once again, the bitmask values varies on a per-chip basis, though the
>> fundamentals are the same.
> 
> Thanks for the explanation.
> 
> Mark.
> 

Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Thomas Gleixner]

On Fri, 5 Sep 2014, Florian Fainelli wrote:
> On 09/05/2014 02:05 AM, Mark Rutland wrote:
> >>>>> +- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
> >>>>> +  wakeup source for system suspend/resume.
> >>>
> >>> How variable is this?
> >>
> >> There's two instances of this interrupt controller on most SoCs, one
> >> that can wake up the system, one that cannot, see below.
> >>
> >>>
> >>> I realise have properties like this elsewhere, but it seems to be
> >>> hacking around the lack of a decent power domain interface for figuring
> >>> this out.
> >>
> >> Humm, I kind of see your point here with the power domains, I don't see
> >> a big problem with specifying that property though, at most this becomes
> >> redundant when we have a power domain representation (which will be very
> >> simple: always-on and everything else).
> > 
> > Sure, we seem to have done that elsewhere.
> > 
> >>>>> +- brcm,int-fwd-mask: if present, a 32-bits bit mask describing the interrupts
> >>>>> +  which need to be enabled in this controller to flow to the higher level
> >>>>> +  interrupt controller. This is typically needed for the UARTs interrupts to
> >>>>> +  flow through the top-level interrupt controller (e.g: ARM GIC on ARM-based
> >>>>> +  platforms).
> >>>>> +
> >>>
> >>> I don't follow why this property is needed at all. Is this a mechanism
> >>> to bypass this controller entirely? Why should this be described as a
> >>> fixed HW property?
> >>
> >> This interrupt controller has traditionally (not necessarily for good
> >> reasons) been the placeholder for special bits that control whether our
> >> UARTs level 1 interrupts (wired to the ARM GIC) will flow to the L1
> >> interrupt.
> > 
> > So basically setting these bits unmasks some irq lines inpout to the
> > GIC?
> 
> Right, this is what happens. We prefer to use the GIC interrupts because
> that provides more flexibility.
> 
> > 
> >> We discussed initially with Arnd Bergman about how to best approach
> >> this, and he was happy with a bitmask since:
> >>
> >> a) that is a one-time initialization thing that can happen anywhere in
> >> the kernel before UART interrupts get used (so before user-space gets
> >> scheduled)
> > 
> > That feels a little dodgy to me, but perhaps that's ok.
> 
> The other approach was to use the "interrupt-extended" property for the
> UART nodes and have them reference both their GIC interrupt, and the
> BCM7120-L2 interrupt, but that also requires UART driver/platform
> modifications to account for that extra "interrupt", on which we are
> only ever going to call enable_irq() and nothing more.
> 
> So, in the end, this turned out to be simpler to just read the
> "brcm,irq-fwd-mask" property and apply it to the relevant register.

So if I understand correctly what you have is:

                          /- GIC------------->   
 Device-irq ---- [routing]
                          \- BC irq chip ---->

and you implement it as

 Device-irq ---- [BC irq chip] ---- [GIC] --->
                            |
                            ----------------->

And the fwd mask is to tell the BC chip to use the GIC and which irq
of the GIC, so it can fiddle with the GIC under the hood, right?

Thanks,

	tglx

Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Florian Fainelli]

On 09/05/2014 12:21 PM, Thomas Gleixner wrote:
> On Fri, 5 Sep 2014, Florian Fainelli wrote:
>> On 09/05/2014 02:05 AM, Mark Rutland wrote:
>>>>>>> +- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
>>>>>>> +  wakeup source for system suspend/resume.
>>>>>
>>>>> How variable is this?
>>>>
>>>> There's two instances of this interrupt controller on most SoCs, one
>>>> that can wake up the system, one that cannot, see below.
>>>>
>>>>>
>>>>> I realise have properties like this elsewhere, but it seems to be
>>>>> hacking around the lack of a decent power domain interface for figuring
>>>>> this out.
>>>>
>>>> Humm, I kind of see your point here with the power domains, I don't see
>>>> a big problem with specifying that property though, at most this becomes
>>>> redundant when we have a power domain representation (which will be very
>>>> simple: always-on and everything else).
>>>
>>> Sure, we seem to have done that elsewhere.
>>>
>>>>>>> +- brcm,int-fwd-mask: if present, a 32-bits bit mask describing the interrupts
>>>>>>> +  which need to be enabled in this controller to flow to the higher level
>>>>>>> +  interrupt controller. This is typically needed for the UARTs interrupts to
>>>>>>> +  flow through the top-level interrupt controller (e.g: ARM GIC on ARM-based
>>>>>>> +  platforms).
>>>>>>> +
>>>>>
>>>>> I don't follow why this property is needed at all. Is this a mechanism
>>>>> to bypass this controller entirely? Why should this be described as a
>>>>> fixed HW property?
>>>>
>>>> This interrupt controller has traditionally (not necessarily for good
>>>> reasons) been the placeholder for special bits that control whether our
>>>> UARTs level 1 interrupts (wired to the ARM GIC) will flow to the L1
>>>> interrupt.
>>>
>>> So basically setting these bits unmasks some irq lines inpout to the
>>> GIC?
>>
>> Right, this is what happens. We prefer to use the GIC interrupts because
>> that provides more flexibility.
>>
>>>
>>>> We discussed initially with Arnd Bergman about how to best approach
>>>> this, and he was happy with a bitmask since:
>>>>
>>>> a) that is a one-time initialization thing that can happen anywhere in
>>>> the kernel before UART interrupts get used (so before user-space gets
>>>> scheduled)
>>>
>>> That feels a little dodgy to me, but perhaps that's ok.
>>
>> The other approach was to use the "interrupt-extended" property for the
>> UART nodes and have them reference both their GIC interrupt, and the
>> BCM7120-L2 interrupt, but that also requires UART driver/platform
>> modifications to account for that extra "interrupt", on which we are
>> only ever going to call enable_irq() and nothing more.
>>
>> So, in the end, this turned out to be simpler to just read the
>> "brcm,irq-fwd-mask" property and apply it to the relevant register.
> 
> So if I understand correctly what you have is:
> 
>                           /- GIC------------->   
>  Device-irq ---- [routing]
>                           \- BC irq chip ---->
> 
> and you implement it as
> 
>  Device-irq ---- [BC irq chip] ---- [GIC] --->
>                             |
>                             ----------------->
> 
> And the fwd mask is to tell the BC chip to use the GIC and which irq
> of the GIC, so it can fiddle with the GIC under the hood, right?

The forward mask really is to tell the BCM7120 l2 interrupt controller:
bypass me, and output the UART interrupts directly at the GIC level, so
I think this does match your understanding.

Not setting the forward mask means you would get the UART interrupts at
the BCM7120 l2 interrupt controller level, and have to handle them here.

Hope this helps clarify what this funky piece of hardware does.
--
Florian

Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Thomas Gleixner]

On Fri, 5 Sep 2014, Florian Fainelli wrote:
> On 09/05/2014 12:21 PM, Thomas Gleixner wrote:
> > So if I understand correctly what you have is:
> > 
> >                           /- GIC------------->   
> >  Device-irq ---- [routing]
> >                           \- BC irq chip ---->
> > 
> > and you implement it as
> > 
> >  Device-irq ---- [BC irq chip] ---- [GIC] --->
> >                             |
> >                             ----------------->
> > 
> > And the fwd mask is to tell the BC chip to use the GIC and which irq
> > of the GIC, so it can fiddle with the GIC under the hood, right?
> 
> The forward mask really is to tell the BCM7120 l2 interrupt controller:
> bypass me, and output the UART interrupts directly at the GIC level, so
> I think this does match your understanding.
> 
> Not setting the forward mask means you would get the UART interrupts at
> the BCM7120 l2 interrupt controller level, and have to handle them here.
> 
> Hope this helps clarify what this funky piece of hardware does.

Sigh, this stacked interrupt chip nonsense is becoming a plague.

So if you set that bit then the UART driver only sees the GIC as its
interrupt controller and not the L2 thingy. So, the L2 chip only
enables its interrupt unconditionally for that line and the
enable/disable happens at the GIC level.

If that's the case, that's fine with me. It's not pretty, but at least
it does not involve L2 fiddling indirectly with the GIC.

Thanks,

	tglx

Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding

[Florian Fainelli]

On 09/05/2014 01:44 PM, Thomas Gleixner wrote:
> On Fri, 5 Sep 2014, Florian Fainelli wrote:
>> On 09/05/2014 12:21 PM, Thomas Gleixner wrote:
>>> So if I understand correctly what you have is:
>>>
>>>                           /- GIC------------->   
>>>  Device-irq ---- [routing]
>>>                           \- BC irq chip ---->
>>>
>>> and you implement it as
>>>
>>>  Device-irq ---- [BC irq chip] ---- [GIC] --->
>>>                             |
>>>                             ----------------->
>>>
>>> And the fwd mask is to tell the BC chip to use the GIC and which irq
>>> of the GIC, so it can fiddle with the GIC under the hood, right?
>>
>> The forward mask really is to tell the BCM7120 l2 interrupt controller:
>> bypass me, and output the UART interrupts directly at the GIC level, so
>> I think this does match your understanding.
>>
>> Not setting the forward mask means you would get the UART interrupts at
>> the BCM7120 l2 interrupt controller level, and have to handle them here.
>>
>> Hope this helps clarify what this funky piece of hardware does.
> 
> Sigh, this stacked interrupt chip nonsense is becoming a plague.

This is a HW design that we inherited, but fortunately we might be able
to fix that in the future.

> 
> So if you set that bit then the UART driver only sees the GIC as its
> interrupt controller and not the L2 thingy. So, the L2 chip only
> enables its interrupt unconditionally for that line and the
> enable/disable happens at the GIC level.

Exactly, this is completely transparent for the UART and the GIC.

> 
> If that's the case, that's fine with me. It's not pretty, but at least
> it does not involve L2 fiddling indirectly with the GIC.

Absolutely, we do not have to do the arch_gic_extn thingy.

Thanks for your feedback!
--
Florian