Re: [PATCH V2] MIPS: bugfix of coherentio variable default setup

[Markos Chandras <Markos.Chandras@imgtec.com>]

Hi Leonid,

On 09/08/2014 08:10 PM, Leonid Yegoshin wrote:
> Patch commit b6d92b4a6bdb880b39789c677b952c53a437028d
> 
>     MIPS: Add option to disable software I/O coherency.
> 
>     Some MIPS controllers have hardware I/O coherency. This patch
>     detects those and turns off software coherency. A new kernel
>     command line option also allows the user to manually turn
>     software coherency on or off.
> 
> in fact enforces L2 cache flushes even on systems with IOCU.
> The default value of coherentio is 0 and is not changed even with IOCU.
> It is a serious performance problem because it destroys all IOCU performance
> advantages.
> 
> It is fixed by setting coherentio to tri-state with default value as (-1) and
> setup a final value during platform coherency setup.
> 
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> [...]
> diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
> index db7c9e5..48039fd 100644
> --- a/arch/mips/mti-malta/malta-setup.c
> +++ b/arch/mips/mti-malta/malta-setup.c
> @@ -147,13 +147,17 @@ static void __init plat_setup_iocoherency(void)
>  	if (plat_enable_iocoherency()) {
>  		if (coherentio == 0)
>  			pr_info("Hardware DMA cache coherency disabled\n");
> -		else
> +		else {
> +			coherentio = 1;
>  			pr_info("Hardware DMA cache coherency enabled\n");
> +		}
>  	} else {
>  		if (coherentio == 1)
>  			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
> -		else
> +		else {
> +			coherentio = 0;
>  			pr_info("Software DMA cache coherency enabled\n");
> +		}

This is not acceptable coding style for the kernel. See
Documentation/CodingStyle, Chapter 3. Since you are adding braces in the
"else" case, you should also add them in the "if" case as well.

-- 
markos