From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753307AbaIVH4W (ORCPT ); Mon, 22 Sep 2014 03:56:22 -0400 Received: from va-smtp01.263.net ([54.88.144.211]:38541 "EHLO vasmtpcom.263.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751270AbaIVH4V (ORCPT ); Mon, 22 Sep 2014 03:56:21 -0400 X-RL-SENDER: kever.yang@rock-chips.com X-FST-TO: linux-arm-kernel@lists.infradead.org X-SENDER-IP: 127.0.0.1 X-LOGIN-NAME: kever.yang@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 1 Message-ID: <541FD619.3060108@rock-chips.com> Date: Mon, 22 Sep 2014 15:56:09 +0800 From: Kever Yang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.0 MIME-Version: 1.0 To: =?windows-1252?Q?Heiko_St=FCbner?= , Mike Turquette CC: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] clk: rockchip: add initcall to set clk defaults after syscons are available References: <1566610.B4NH8lpaoI@diego> In-Reply-To: <1566610.B4NH8lpaoI@diego> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Heiko, On 08/07/2014 08:57 PM, Heiko Stübner wrote: > PLLs on Rockchip platforms report their locking state in an external > register situated in the "General Register Files" which is provided > through a syscon device. > > When the initial clk init runs, this syscon is of course not yet > available, making it impossible to set PLLs to other frequencies > through the assigned-rate property of the clock-controller node. > > Syscon devices are initialized through a postcore initcall, so add an > arch_initcall to rerun the rockchip specific clock initalization when > the GRF is available. > > As the clock init already runs two times (through of_clk_add_provider > and of_clk_init), a third time shouldn't hurt to much and in the best > case wouldn't change any settings at all. > > Signed-off-by: Heiko Stuebner > --- > drivers/clk/rockchip/clk.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c > index 9a3adb1..e14b108 100644 > --- a/drivers/clk/rockchip/clk.c > +++ b/drivers/clk/rockchip/clk.c > @@ -23,6 +23,7 @@ > #include > #include > #include > +#include > #include > #include > #include "clk.h" > @@ -126,6 +127,18 @@ void __init rockchip_clk_init(struct device_node *np, void __iomem *base, > of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); > } > > +/** > + * Set clock-defaults again, after grf regmap is available for PLLs. > + */ > +static int __init rockchip_clk_set_defaults(void) > +{ > + if (cru_node) > + return of_clk_set_defaults(cru_node, true); > + > + return 0; > +} > +arch_initcall(rockchip_clk_set_defaults); > + > struct regmap *rockchip_clk_get_grf(void) > { > if (IS_ERR(grf)) This patch works on my rk3288 evb, so, Tested-by: Kever Yang