From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753514AbaIZCMz (ORCPT ); Thu, 25 Sep 2014 22:12:55 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:59574 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752913AbaIZCMw (ORCPT ); Thu, 25 Sep 2014 22:12:52 -0400 Message-ID: <5424CB70.9020800@huawei.com> Date: Fri, 26 Sep 2014 10:12:00 +0800 From: Yijing Wang User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 To: Thierry Reding CC: Bjorn Helgaas , , , Xinwei Hu , Wuyun , , Russell King , , , , , Arnd Bergmann , Thomas Gleixner , "Konrad Rzeszutek Wilk" , , Joerg Roedel , , , Benjamin Herrenschmidt , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , "Sergei Shtylyov" , Michael Ellerman , Thomas Petazzoni Subject: Re: [PATCH v2 12/22] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <1411614872-4009-13-git-send-email-wangyijing@huawei.com> <20140925073435.GJ12423@ulmo> In-Reply-To: <20140925073435.GJ12423@ulmo> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.27.212] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2014/9/25 15:34, Thierry Reding wrote: > On Thu, Sep 25, 2014 at 11:14:22AM +0800, Yijing Wang wrote: > [...] >> diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c > [...] >> @@ -132,12 +132,12 @@ msi_irq_allocated: >> /* Make sure the search for available interrupts didn't fail */ >> if (irq >= 64) { >> if (request_private_bits) { >> - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one", >> + pr_err("octeon_setup_msi_irq: Unable to find %d free interrupts, trying just one", >> 1 << request_private_bits); > > Perhaps while at it make this (and other similar changes in this patch): > > pr_err("%s(): Unable to ...", __func__, ...); Will update it, thanks! > > So that it becomes more resilient against this kind of rename? > >> request_private_bits = 0; >> goto try_only_one; >> } else >> - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); >> + panic("octeon_setup_msi_irq: Unable to find a free MSI interrupt"); > >> @@ -210,14 +210,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) >> >> return 0; >> } >> - > > This... OK > >> @@ -240,7 +239,7 @@ void arch_teardown_msi_irq(unsigned int irq) >> */ >> number_irqs = 0; >> while ((irq0 + number_irqs < 64) && >> - (msi_multiple_irq_bitmask[index] >> + (msi_multiple_irq_bitmask[index] > > ... and this seem like unrelated whitespace changes. OK > >> & (1ull << (irq0 + number_irqs)))) >> number_irqs++; >> number_irqs++; >> @@ -249,8 +248,8 @@ void arch_teardown_msi_irq(unsigned int irq) >> /* Shift the mask to the correct bit location */ >> bitmask <<= irq0; >> if ((msi_free_irq_bitmask[index] & bitmask) != bitmask) >> - panic("arch_teardown_msi_irq: Attempted to teardown MSI " >> - "interrupt (%d) not in use", irq); >> + panic("octeon_teardown_msi_irq: Attempted to teardown MSI " >> + "interrupt (%d) not in use", irq); > > And the second line here also needlessly changes the indentation. OK > > Thierry > -- Thanks! Yijing