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Thu, 26 Sep 2024 15:50:59 -0700 (PDT) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b26515ef9sm403643b3a.134.2024.09.26.15.50.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Sep 2024 15:50:59 -0700 (PDT) Message-ID: <543df2e3-dcb4-4a5d-b781-e2b39d62715a@broadcom.com> Date: Thu, 26 Sep 2024 15:50:57 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] tty: rp2: Fix reset with non forgiving PCIe host bridges To: Jiri Slaby , linux-serial@vger.kernel.org Cc: Jim Quinlan , Kevin Cernekee , Greg Kroah-Hartman , John Ogness , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Thomas Gleixner , "open list:TTY LAYER AND SERIAL DRIVERS" References: <20240906225435.707837-1-florian.fainelli@broadcom.com> <051fdbe1-e5d9-4d5d-bc1a-921d8d3d4a9e@kernel.org> Content-Language: en-US From: Florian Fainelli Autocrypt: addr=florian.fainelli@broadcom.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 9/23/24 02:44, Jiri Slaby wrote: > On 07. 09. 24, 0:54, Florian Fainelli wrote: >> The write to RP2_GLOBAL_CMD followed by an immediate read of >> RP2_GLOBAL_CMD in rp2_reset_asic() is intented to flush out the write, >> however by then the device is already in reset and cannot respond to a >> memory cycle access. >> >> On platforms such as the Raspberry Pi 4 and others using the >> pcie-brcmstb.c driver, any memory access to a device that cannot respond >> is met with a fatal system error, rather than being substituted with all >> 1s as is usually the case on PC platforms. >> >> Swapping the delay and the read ensures that the device has finished >> resetting before we attempt to read from it. >> >> Fixes: 7d9f49afa451 ("serial: rp2: New driver for Comtrol RocketPort 2 >> cards") >> Suggested-by: Jim Quinlan >> Signed-off-by: Florian Fainelli >> --- >>   drivers/tty/serial/rp2.c | 2 +- >>   1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/tty/serial/rp2.c b/drivers/tty/serial/rp2.c >> index 4132fcff7d4e..8bab2aedc499 100644 >> --- a/drivers/tty/serial/rp2.c >> +++ b/drivers/tty/serial/rp2.c >> @@ -577,8 +577,8 @@ static void rp2_reset_asic(struct rp2_card *card, >> unsigned int asic_id) >>       u32 clk_cfg; >>       writew(1, base + RP2_GLOBAL_CMD); >> -    readw(base + RP2_GLOBAL_CMD); >>       msleep(100); >> +    readw(base + RP2_GLOBAL_CMD); > > The read was there to force PCI posting to really flush the write to the > device before the sleep (and not to post). How is this ensured now? (In > fact, instead of the move, you could have deleted it completely.) > > Can you actually read another register which a resetting device would > reply? Sure I can do that, give me a couple more days to get back to you. -- Florian