[PATCH 0/2] Marvell Armada 375/38x MPIC/MSI fixes

[PATCH 0/2] Marvell Armada 375/38x MPIC/MSI fixes

[Grzegorz Jaszczyk]

This patchset contains a set of fixes for issues found while doing some test
with different interrupts configuration on Armada 375 and Armada 38x Marvell
SoCs. The patches were tested and apply on v3.17-rc6.

Any feedback is welcome.

Grzegorz Jaszczyk (2):
  irqchip: armada-370-xp: fix MSI interrupt handling
  irqchip: armada-370-xp: fix MPIC interrupt handling

 drivers/irqchip/irq-armada-370-xp.c | 23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

-- 
1.8.3.1

[PATCH 1/2] irqchip: armada-370-xp: fix MSI interrupt handling

[Grzegorz Jaszczyk]

The MSI interrupts use the 16 high doorbells, which are notified by using IRQ1
of the main interrupt controller.

The MSI interrupts were handled correctly for Armada-XP and Armada-370 but not
for Armada-375 and Armada-38x, which use chained handler for the MPIC.

This commit fixes that by checking proper interrupt number in chained handler
for the MPIC.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/irqchip/irq-armada-370-xp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 574aba0..91424c4 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -417,9 +417,9 @@ static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
 
 	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
 
-	if (irqmap & BIT(0)) {
+	if (irqmap & BIT(1)) {
 		armada_370_xp_handle_msi_irq(NULL, true);
-		irqmap &= ~BIT(0);
+		irqmap &= ~BIT(1);
 	}
 
 	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
-- 
1.8.3.1

[PATCH 2/2] irqchip: armada-370-xp: fix MPIC interrupt handling

[Grzegorz Jaszczyk]

In both Armada-375 and Armada-38x MPIC interrupts should be identified by
reading cause register multiplied by the interrupt mask.

A lack of above mentioned multiplication resulted in a bug, caused by the
fact that in Armada-375 and Armada-38x some of the interrupts
(e.g. network interrupts) can be handled either as a GIC or MPIC interrupts.
Therefore during MPIC interrupts handling, cause register shows hits from
interrupts even if they are masked for MPIC but unmasked for a GIC.

This resulted in 'bad IRQ' error, because masked MPIC interrupt without
registered interrupt handler, was trying to be handled during interrupt
handling procedure of some other unmasked MPIC interrupt (e.g. local timer
irq).

This commit fixes that by ensuring that during MPIC interrupt handling only
interrupts that are unmasked for MPIC are processed.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/irqchip/irq-armada-370-xp.c | 23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 91424c4..1cb538f 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -43,6 +43,7 @@
 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
+#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
 
 #define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
 #define ARMADA_375_PPI_CAUSE			(0x10)
@@ -410,19 +411,29 @@ static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
 						  struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_get_chip(irq);
-	unsigned long irqmap, irqn;
+	unsigned long irqmap, irqn, irqsrc, cpuid;
 	unsigned int cascade_irq;
 
 	chained_irq_enter(chip, desc);
 
 	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
-
-	if (irqmap & BIT(1)) {
-		armada_370_xp_handle_msi_irq(NULL, true);
-		irqmap &= ~BIT(1);
-	}
+	cpuid = cpu_logical_map(smp_processor_id());
 
 	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
+		irqsrc = readl_relaxed(main_int_base +
+				       ARMADA_370_XP_INT_SOURCE_CTL(irqn));
+
+		/* Check if the interrupt is not masked on current CPU.
+		 * Test IRQ (0-1) and FIQ (8-9) mask bits.
+		 */
+		if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
+			continue;
+
+		if (irqn == 1) {
+			armada_370_xp_handle_msi_irq(NULL, true);
+			continue;
+		}
+
 		cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
 		generic_handle_irq(cascade_irq);
 	}
-- 
1.8.3.1

Re: [PATCH 0/2] Marvell Armada 375/38x MPIC/MSI fixes

[Ezequiel Garcia]

Jason,

On 25 Sep 01:17 PM, Grzegorz Jaszczyk wrote:
> This patchset contains a set of fixes for issues found while doing some test
> with different interrupts configuration on Armada 375 and Armada 38x Marvell
> SoCs. The patches were tested and apply on v3.17-rc6.
> 
> Any feedback is welcome.
> 
> Grzegorz Jaszczyk (2):
>   irqchip: armada-370-xp: fix MSI interrupt handling
>   irqchip: armada-370-xp: fix MPIC interrupt handling

The second patch fixes an unhandled IRQ storm triggered by the mvpp2
ethernet driver, when the kernel is built with CONFIG_SMP=n.

When any network activity is attempted the kernel is interrupted by a per-cpu 
IRQ (which is not the one the driver expects). The interrupt is not mapped 
into Linux's virtual IRQ space, so the result is:

  irq 0, desc: ee004000, depth: 1, count: 0, unhandled: 0
  ->handle_irq():  c00466e8, handle_bad_irq+0x0/0x260
  ->irq_data.chip(): c1181460, 0xc1181460
  ->action():   (null)
     IRQ_NOPROBE set
   IRQ_NOREQUEST set

For both patches:

Fixes: bc69b8adfe22 ("irqchip: armada-370-xp: Setup a chained handler for the MPIC")
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>

Thanks,
-- 
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com

Re: [PATCH 0/2] Marvell Armada 375/38x MPIC/MSI fixes

[Jason Cooper]

On Thu, Sep 25, 2014 at 01:17:17PM +0200, Grzegorz Jaszczyk wrote:
> This patchset contains a set of fixes for issues found while doing some test
> with different interrupts configuration on Armada 375 and Armada 38x Marvell
> SoCs. The patches were tested and apply on v3.17-rc6.
> 
> Any feedback is welcome.
> 
> Grzegorz Jaszczyk (2):
>   irqchip: armada-370-xp: fix MSI interrupt handling
>   irqchip: armada-370-xp: fix MPIC interrupt handling
> 
>  drivers/irqchip/irq-armada-370-xp.c | 23 +++++++++++++++++------
>  1 file changed, 17 insertions(+), 6 deletions(-)

Ah crap.  This slipped off my plate.  Sorry about that.  I've now
applied these to irqchip/urgent with Ezequiel's Ack.  I'll get them into
-next and hopefully do a PR toward the end of next week.

thx,

Jason.

Re: [PATCH 0/2] Marvell Armada 375/38x MPIC/MSI fixes

[Ezequiel Garcia]

On 10/03/2014 10:50 AM, Jason Cooper wrote:
> On Thu, Sep 25, 2014 at 01:17:17PM +0200, Grzegorz Jaszczyk wrote:
>> This patchset contains a set of fixes for issues found while doing some test
>> with different interrupts configuration on Armada 375 and Armada 38x Marvell
>> SoCs. The patches were tested and apply on v3.17-rc6.
>>
>> Any feedback is welcome.
>>
>> Grzegorz Jaszczyk (2):
>>   irqchip: armada-370-xp: fix MSI interrupt handling
>>   irqchip: armada-370-xp: fix MPIC interrupt handling
>>
>>  drivers/irqchip/irq-armada-370-xp.c | 23 +++++++++++++++++------
>>  1 file changed, 17 insertions(+), 6 deletions(-)
> 
> Ah crap.  This slipped off my plate.  Sorry about that.  I've now
> applied these to irqchip/urgent with Ezequiel's Ack.  I'll get them into
> -next and hopefully do a PR toward the end of next week.
> 

Jason,

The patches don't seem to be in v3.18-rc1 for some reason.

I can't seem to find your PR (probably because I've switched to
Thunderbird now
and it's a pain to search mails properly).

Since this is an important fix, maybe you can schedule it for -rc2?

Thanks!
-- 
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com

Re: [PATCH 0/2] Marvell Armada 375/38x MPIC/MSI fixes

[Jason Cooper]

On Tue, Oct 21, 2014 at 11:19:31AM -0300, Ezequiel Garcia wrote:
> On 10/03/2014 10:50 AM, Jason Cooper wrote:
> > On Thu, Sep 25, 2014 at 01:17:17PM +0200, Grzegorz Jaszczyk wrote:
> >> This patchset contains a set of fixes for issues found while doing some test
> >> with different interrupts configuration on Armada 375 and Armada 38x Marvell
> >> SoCs. The patches were tested and apply on v3.17-rc6.
> >>
> >> Any feedback is welcome.
> >>
> >> Grzegorz Jaszczyk (2):
> >>   irqchip: armada-370-xp: fix MSI interrupt handling
> >>   irqchip: armada-370-xp: fix MPIC interrupt handling
> >>
> >>  drivers/irqchip/irq-armada-370-xp.c | 23 +++++++++++++++++------
> >>  1 file changed, 17 insertions(+), 6 deletions(-)
> > 
> > Ah crap.  This slipped off my plate.  Sorry about that.  I've now
> > applied these to irqchip/urgent with Ezequiel's Ack.  I'll get them into
> > -next and hopefully do a PR toward the end of next week.
> > 
> 
> Jason,
> 
> The patches don't seem to be in v3.18-rc1 for some reason.

Correct.

> I can't seem to find your PR (probably because I've switched to
> Thunderbird now
> and it's a pain to search mails properly).

Some folks seem to like Claws.  There hasn't been a PR yet, though.

> Since this is an important fix, maybe you can schedule it for -rc2?

I have.  For some reason I have yet to delve into, there were no
linux-next's during the merge window.  As a result, yesterday's -next
was the first for the two patches in question.  I'd like to get them
pushed for -rc2, so I'll probably send the PR tomorrow to get one more
day in -next.

thx,

Jason.

Re: [PATCH 0/2] Marvell Armada 375/38x MPIC/MSI fixes

[Ezequiel Garcia]

On 10/21/2014 12:14 PM, Jason Cooper wrote:
[..]
> 
>> Since this is an important fix, maybe you can schedule it for -rc2?
> 
> I have.  For some reason I have yet to delve into, there were no
> linux-next's during the merge window.  As a result, yesterday's -next
> was the first for the two patches in question.  I'd like to get them
> pushed for -rc2, so I'll probably send the PR tomorrow to get one more
> day in -next.
> 

Great, thanks!
-- 
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com