Re: [PATCH] x86: remove arbitrary instruction size limit in instruction decoder

[Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>]

(2014/11/18 5:49), Dave Hansen wrote:
> On 11/13/2014 06:49 AM, Masami Hiramatsu wrote:
>> (2014/11/13 7:53), Dave Hansen wrote:
>>> The kprobes code probably needs to be looked at here a bit more
>>> carefully.  This patch still respects the MAX_INSN_SIZE limit
>>> there but the kprobes code does look like it might be able to
>>> be a bit more strict than it currently is.
>>
>> Would you mean kprobes can copy shorter? Maybe, but I think current
>> one is enough because it is on a cold path.
>> OK, at least this looks good to me.
> 
> As it stands now, if you happened to be decoding an instruction which is
> short and it was *JUST* before a memory hole, I think it could oops the
> kernel.
> 
> This doesn't look like it is very common (or maybe even possible) in
> practice.

OK, then I'll add a check whether the end address is also in kernel_text.
(we've done it for the start address)

> 
>>> Note: the v10 version of the MPX patches I just posted depends
>>> on this patch.
>>
>> BTW, current insn decoder doesn't support MPX... That should be
>> updated (add bnd* to x86-insn-map.txt)
> 
> I think they're in there already:
> 
>> grep -i bnd arch/x86/lib/x86-opcode-map.txt
> 1a: BNDCL Ev,Gv | BNDCU Ev,Gv | BNDMOV Gv,Ev | BNDLDX Gv,Ev,Gv
> 1b: BNDCN Ev,Gv | BNDMOV Ev,Gv | BNDMK Gv,Ev | BNDSTX Ev,GV,Gv
> 
> Or were there others you were thinking of?

Ah, I misunderstood that AVX512 etc...

Thank you,

-- 
Masami HIRAMATSU
Software Platform Research Dept. Linux Technology Research Center
Hitachi, Ltd., Yokohama Research Laboratory
E-mail: masami.hiramatsu.pt@hitachi.com