Re: [PATCH v2] X86-32: Allocate 256 bytes for pgd in PAE paging

[Dave Hansen <dave.hansen@intel.com>]

On 12/17/2014 01:47 PM, Fenghua Yu wrote:
> +static inline pgd_t *_pgd_alloc(void)
> +{
> +#if defined(CONFIG_X86_PAE) && !defined(CONFIG_XEN)
> +	return kmalloc(sizeof(pgdval_t) * PTRS_PER_PGD, PGALLOC_GFP);
> +#else
> +	return (pgd_t *)__get_free_page(PGALLOC_GFP);
> +#endif
> +}

I'm looking at:

	"Figure 4-7. Formats of CR3 and Paging-Structure Entries with
	 PAE Paging"

in the SDM.  It makes it pretty clear that the lower 5 bits of cr3 are
ignored in PAE mode.  That means we have to be 32-byte (or greater)
aligned, right?  Does kmalloc() guarantee that?

IOW, do *ALL* of the sl*b allocators in all of their forms with all of
their debugging options guarantee 32-byte alignment when allocating
256-byte objects?

I know we at least try to align to a cacheline, which would be good
enough, but I'm fuzzy on what we *guarantee*.