From: James Hogan <james.hogan@imgtec.com>
To: Andrew Bresticker <abrestic@chromium.org>,
Ralf Baechle <ralf@linux-mips.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>,
Markos Chandras <markos.chandras@imgtec.com>,
Paul Burton <paul.burton@imgtec.com>,
"Qais Yousef" <qais.yousef@imgtec.com>,
Jonas Gorski <jogo@openwrt.org>,
"John Crispin" <blogic@openwrt.org>,
David Daney <ddaney.cavm@gmail.com>, <linux-mips@linux-mips.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V2 18/24] irqchip: mips-gic: Stop using per-platform mapping tables
Date: Thu, 15 Jan 2015 16:29:26 +0000 [thread overview]
Message-ID: <54B7EAE6.8040503@imgtec.com> (raw)
In-Reply-To: <54B7AB95.4080501@imgtec.com>
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On 15/01/15 11:59, James Hogan wrote:
> Hi Andrew,
>
> On 18/09/14 22:47, Andrew Bresticker wrote:
>> Now that the GIC properly uses IRQ domains, kill off the per-platform
>> routing tables that were used to make the GIC appear transparent.
>>
>> This includes:
>> - removing the mapping tables and the support for applying them,
>> - moving GIC IPI support to the GIC driver,
>> - properly routing the i8259 through the GIC on Malta, and
>> - updating IRQ assignments on SEAD-3 when the GIC is present.
>>
>> Platforms no longer will pass an interrupt mapping table to gic_init.
>> Instead, they will pass the CPU interrupt vector (2 - 7) that they
>> expect the GIC to route interrupts to. Note that in EIC mode this
>> value is ignored and all GIC interrupts are routed to EIC vector 1.
>>
>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>> Acked-by: Jason Cooper <jason@lakedaemon.net>
>> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
>> Tested-by: Qais Yousef <qais.yousef@imgtec.com>
>
> This commit (18743d2781d01d34d132f952a2e16353ccb4c3de) appears to break
> boot of interAptiv, dual core, dual vpe per core, on malta with
> malta_defconfig.
>
> It gets to here:
> ...
> CPU1 revision is: 0001a120 (MIPS interAptiv (multi))
> FPU revision is: 0173a000
> Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes.
> Primary data cache 64kB, 4-way, PIPT, no aliases, linesize 32 bytes
> MIPS secondary cache 1024kB, 8-way, linesize 32 bytes.
> Synchronize counters for CPU 1: done.
> Brought up 2 CPUs
>
> and then appears to just hang. Passing nosmp works around it, allowing
> it to get to userland.
>
> Is that a problem you've already come across?
>
> I'll keep debugging.
Right, it appears the CPU IRQ line that the GIC is using doesn't get
unmasked (STATUSF_IP2) when a new VPE is brought up, so only the first
CPU will actually get any interrupts after your patch (including the
rather critical IPIs), i.e. hacking it in vsmp_init_secondary() in
smp-mt.c allows it to boot.
Hmm, I'll have a think about what the most generic fix is, since
arbitrary stuff may or may not have registered handlers for the raw CPU
interrupts (timer, performance counter, gic etc)...
Cheers
James
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next prev parent reply other threads:[~2015-01-15 16:29 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-18 21:47 [PATCH V2 00/24] MIPS GIC cleanup, part 1 Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 01/24] MIPS: Always use IRQ domains for CPU IRQs Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 02/24] MIPS: Rename mips_cpu_intc_init() -> mips_cpu_irq_of_init() Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 03/24] MIPS: Provide a generic plat_irq_dispatch Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 04/24] MIPS: Set vint handler when mapping CPU interrupts Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 05/24] MIPS: i8259: Use IRQ domains Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 06/24] MIPS: Add hook to get C0 performance counter interrupt Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 07/24] MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 08/24] MIPS: Remove gic_{enable,disable}_interrupt() Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 09/24] MIPS: sead3: Remove sead3-serial.c Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 10/24] MIPS: sead3: Do not overlap CPU/GIC IRQ ranges Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 11/24] MIPS: Malta: Move MSC01 interrupt base Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 12/24] MIPS: Move MIPS_GIC_IRQ_BASE into platform irq.h Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 13/24] MIPS: Move GIC to drivers/irqchip/ Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 14/24] irqchip: mips-gic: Remove platform irq_ack/irq_eoi callbacks Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 15/24] irqchip: mips-gic: Implement irq_set_type callback Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 16/24] irqchip: mips-gic: Fix gic_set_affinity() return value Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 17/24] irqchip: mips-gic: Use IRQ domains Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 18/24] irqchip: mips-gic: Stop using per-platform mapping tables Andrew Bresticker
2015-01-15 11:59 ` James Hogan
2015-01-15 16:29 ` James Hogan [this message]
2015-01-15 16:36 ` Qais Yousef
2015-01-15 16:50 ` James Hogan
2015-01-15 16:58 ` Andrew Bresticker
2015-01-15 17:25 ` James Hogan
2014-09-18 21:47 ` [PATCH V2 19/24] irqchip: mips-gic: Probe for number of external interrupts Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 20/24] irqchip: mips-gic: Use separate edge/level irq_chips Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 21/24] irqchip: mips-gic: Support local interrupts Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 22/24] irqchip: mips-gic: Remove unnecessary globals Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 23/24] MIPS: Malta: Use generic plat_irq_dispatch Andrew Bresticker
2014-09-18 21:47 ` [PATCH V2 24/24] MIPS: sead3: " Andrew Bresticker
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