From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752260AbbAPVeJ (ORCPT ); Fri, 16 Jan 2015 16:34:09 -0500 Received: from mail-qc0-f177.google.com ([209.85.216.177]:62084 "EHLO mail-qc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751492AbbAPVeH (ORCPT ); Fri, 16 Jan 2015 16:34:07 -0500 Message-ID: <54B983CC.6090507@linaro.org> Date: Fri, 16 Jan 2015 16:34:04 -0500 From: David Long User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 To: Pratyush Anand CC: "linux-arm-kernel@lists.infradead.org" , Russell King , Sandeepa Prabhu , William Cohen , Steve Capper , Catalin Marinas , Will Deacon , "Jon Medhurst (Tixy)" , Masami Hiramatsu , Ananth N Mavinakayanahalli , Anil S Keshavamurthy , davem@davemloft.net, linux-kernel@vger.kernel.org, Pratyush Anand Subject: Re: [PATCH v4 4/6] arm64: Kprobes instruction simulation support References: <1420949002-3726-1-git-send-email-dave.long@linaro.org> <1420949002-3726-5-git-send-email-dave.long@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/14/15 04:32, Pratyush Anand wrote: > On Sun, Jan 11, 2015 at 9:33 AM, David Long wrote: >> From: Sandeepa Prabhu >> >> Add support for AArch64 instruction simulation in kprobes. >> >> Kprobes needs simulation of instructions that cannot be stepped >> from different memory location, e.g.: those instructions >> that uses PC-relative addressing. In simulation, the behaviour >> of the instruction is implemented using a copy of pt_regs. >> >> Following instruction catagories are simulated: >> - All branching instructions(conditional, register, and immediate) >> - Literal access instructions(load-literal, adr/adrp) >> >> Conditional execution is limited to branching instructions in >> ARM v8. If conditions at PSTATE do not match the condition fields >> of opcode, the instruction is effectively NOP. Kprobes considers >> this case as 'miss'. >> changes since v3: >> from David A. Long: >> 1) Fix incorrect simulate_ldrsw_literal() semantics. >> 2) Use instruction test functions instead of private parse table. >> from Will Cohen: >> 3) Remove PC adjustments when simulating an instruction. >> 4) Fix displacement calculations. >> >> Signed-off-by: Sandeepa Prabhu >> Signed-off-by: William Cohen >> Signed-off-by: David A. Long >> --- > > [...] > >> static bool aarch64_insn_is_steppable(u32 insn) >> { >> @@ -60,6 +130,32 @@ arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi) >> */ >> if (aarch64_insn_is_steppable(insn)) >> return INSN_GOOD; >> + >> + asi->prepare = prepare_none; >> + >> + if (aarch64_insn_is_bcond(insn)) { >> + asi->prepare = prepare_bcond; >> + asi->handler = simulate_b_cond; >> + } else if (aarch64_insn_is_cb(insn)) { >> + asi->prepare = prepare_cbz_cbnz; >> + asi->handler = simulate_cbz_cbnz; >> + } else if (aarch64_insn_is_tb(insn)) { >> + asi->prepare = prepare_tbz_tbnz; >> + asi->handler = simulate_tbz_tbnz; >> + } else if (aarch64_insn_is_adr(insn)) > > aarch64_insn_is_adr should be modified to aarch64_insn_is_adr_adrp Yes. >> + asi->handler = simulate_adr_adrp; >> + else if (aarch64_insn_is_b_bl(insn)) >> + asi->handler = simulate_b_bl; >> + else if (aarch64_insn_is_ldr_lit(insn)) >> + asi->handler = simulate_ldr_literal; >> + else if (aarch64_insn_is_ldrsw_lit(insn)) >> + asi->handler = simulate_ldrsw_literal; > > also > > else if (aarch64_insn_is_br_blr(insn) || aarch64_insn_is_ret(insn)) > asi->handler = simulate_br_blr_ret; Yes. > > ~Pratyush > -dl