linux-next: manual merge of the drm tree with Linus' tree

Stephen Rothwell
2024-11-11T02:04:51Z

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Hi all,

Today's linux-next merge of the drm tree got a conflict in:

drivers/gpu/drm/xe/xe_gt_ccs_mode.c

between commit:

7fd3fa006fa5 ("drm/xe: Set mask bits for CCS_MODE register")

from Linus' tree and commit:

a851edc457ed ("drm/xe/ccs_mode: Convert register access to use xe_mmio")

from the drm tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

--
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/xe/xe_gt_ccs_mode.c
index ffcbd05671fc,9360ac4de489..000000000000
--- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
+++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
@@@ -68,13 -68,7 +68,13 @@@ static void __xe_gt_apply_ccs_mode(stru
}
}

+ /*
+ * Mask bits need to be set for the register. Though only Xe2+
+ * platforms require setting of mask bits, it won't harm for older
+ * platforms as these bits are unused there.
+ */
+ mode |= CCS_MODE_CSLICE_0_3_MASK << 16;
- xe_mmio_write32(gt, CCS_MODE, mode);
+ xe_mmio_write32(&gt->mmio, CCS_MODE, mode);

xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
mode, config, num_engines, num_slices);

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