From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933475AbbBBOJA (ORCPT ); Mon, 2 Feb 2015 09:09:00 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:36499 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932206AbbBBOI5 (ORCPT ); Mon, 2 Feb 2015 09:08:57 -0500 X-AuditID: cbfee691-f79b86d000004a5a-ee-54cf84d87c10 Message-id: <54CF84D8.7070208@samsung.com> Date: Mon, 02 Feb 2015 23:08:24 +0900 From: Chanwoo Choi User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-version: 1.0 To: Sylwester Nawrocki Cc: tomasz.figa@gmail.com, mturquette@linaro.org, kgene@kernel.org, pankaj.dubey@samsung.com, sangbae90.lee@samsung.com, inki.dae@samsung.com, chanho61.park@samsung.com, sw0312.kim@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 01/13] clk: samsung: exynos5433: Add binding document for Exynos5433 clock domains References: <1422882074-19758-1-git-send-email-cw00.choi@samsung.com> <1422882074-19758-2-git-send-email-cw00.choi@samsung.com> <54CF81DE.3010902@samsung.com> In-reply-to: <54CF81DE.3010902@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKIsWRmVeSWpSXmKPExsWyRsSkSPdmy/kQg0f7mSwu79e2mHR/AotF /+PXzBaXd81hs5hxfh+TxdMJF9ksFm39wm5x+E07q8XxTwdZLGZMfslmsWrXH0YHbo+ds+6y e2xa1cnmcefaHjaPvi2rGD0+b5ILYI3isklJzcksSy3St0vgyrgybTdrwTznik9dvxkbGLuN uhg5OSQETCS+/5nMBmGLSVy4tx7I5uIQEljKKLGnpZ8dpmjXn34miMR0RokdP06xQjivGSUm LH7KCFLFK6Al8eHRTbAOFgFVicd3PjGD2GxA8f0vboCtEBUIk1g5/QoLRL2gxI/J98BsEQF9 iSWrLoLVMAu0M0lsOpELYgsLZEsc+D4LbKaQwCJGiffXRUBsTgFtienPzgPVcwDV60ncv6gF 0SovsXnNW2aQ2yQE3rJLtJ9ezwhxj4DEt8mHWEDqJQRkJTYdYIZ4TFLi4IobLBMYxWYhuWgW wtRZSKYuYGRexSiaWpBcUJyUXmSqV5yYW1yal66XnJ+7iREYm6f/PZu4g/H+AetDjAIcjEo8 vBbvz4UIsSaWFVfmHmI0BTpiIrOUaHI+MAHklcQbGpsZWZiamBobmVuaKYnz6kj/DBYSSE8s Sc1OTS1ILYovKs1JLT7EyMTBKdXAGOnyrb3Ce2nBdF0vl3WsF5nuVt9xOnnl1/pbb5Vv25QJ LpAs2LbBuEH92mmx7n/uk7YueFjEK+e8ypz1YGxH+q3mB34xCVumnxc95nFOkd9SuJC1QXLG W5/aqyu3cMwKX6XXbv7b1+/xytfHZ4ctKPYKdXOonaQ7Y0dI8IK88FNdHxZ0vJtmo8RSnJFo qMVcVJwIADm3QKjIAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPIsWRmVeSWpSXmKPExsVy+t9jQd0bLedDDO5OMrW4vF/bYtL9CSwW /Y9fM1tc3jWHzWLG+X1MFk8nXGSzWLT1C7vF4TftrBbHPx1ksZgx+SWbxapdfxgduD12zrrL 7rFpVSebx51re9g8+rasYvT4vEkugDWqgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+g0JYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYG aCBhDWPGlWm7WQvmOVd86vrN2MDYbdTFyMkhIWAisetPPxOELSZx4d56ti5GLg4hgemMEjt+ nGKFcF4zSkxY/JQRpIpXQEviw6Ob7CA2i4CqxOM7n5hBbDag+P4XN9hAbFGBMImV06+wQNQL SvyYfA/MFhHQl1iy6iJYDbNAO5PEphO5ILawQLbEge+zwGYKCSxilHh/XQTE5hTQlpj+7DxQ PQdQvZ7E/YtaEK3yEpvXvGWewCgwC8mGWQhVs5BULWBkXsUomlqQXFCclJ5rqFecmFtcmpeu l5yfu4kRHPnPpHYwrmywOMQowMGoxMNr8f5ciBBrYllxZe4hRgkOZiURXg2L8yFCvCmJlVWp RfnxRaU5qcWHGE2B/p/ILCWanA9MSnkl8YbGJmZGlkbmhhZGxuZK4rxK9m0hQgLpiSWp2amp BalFMH1MHJxSDYyuu/dYH7zNuWf67w+zTLf/Ktd02HG3I6Xx8I+MzDm3PGNdm6cnCvY3Z/48 OzXU5OSx/KqsP3f2K5xKd+m9uHTBrAMZD6QOXbls+Gi5qY9OtsAexUXc0qynld0KD2t0/mY4 LVK313tN0pM5l15tOTLtW0yvfJDygvX3726+GvzfTX/Xk6xu3aWLlFiKMxINtZiLihMBhpcW NBIDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sylwester, On 02/02/2015 10:55 PM, Sylwester Nawrocki wrote: > Hi Chanwoo, > > On 02/02/15 14:01, Chanwoo Choi wrote: >> This patch adds devicetree binding document for Exynos5433 SoC system clock >> controller. >> >> Cc: Sylwester Nawrocki >> Cc: Tomasz Figa >> Signed-off-by: Chanwoo Choi >> Acked-by: Inki Dae >> --- >> .../devicetree/bindings/clock/exynos5433-clock.txt | 258 +++++++++++++++++++++ >> 1 file changed, 258 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt >> new file mode 100644 >> index 0000000..2d7a723 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt >> @@ -0,0 +1,258 @@ >> +* Samsung Exynos5433 CMU (Clock Management Units) >> + >> +The Exynos5433 clock controller generates and supplies clock to various >> +controllers within the Exynos5433 SoC. >> + >> +Required Properties: >> + >> +- compatible: should be one of the following. >> + - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP >> + which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS >> + domains and bus clocks. >> + - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF >> + which generates clocks for LLI (Low Latency Interface) IP. >> + - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF >> + which generates clocks for DRAM Memory Controller domain. >> + - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC >> + which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. >> + - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS >> + which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. >> + - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS >> + which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. >> + - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D >> + which generates clocks for G2D/MDMA IPs. >> + - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP >> + which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. >> + - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD >> + which generates clocks for Cortex-A5/BUS/AUDIO clocks. >> + - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" >> + and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS >> + which generates global data buses clock and global peripheral buses clock. >> + - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D >> + which generates clocks for 3D Graphics Engine IP. >> + - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL >> + which generates clocks for GSCALER IPs. >> + >> +- reg: physical base address of the controller and length of memory mapped >> + region. >> + >> +- #clock-cells: should be 1. > > Thanks for addressing my comments! It looks almost good enough, can you > just please also add clocks, clock-names to the list of required properties ? > I guess it's sufficient to mention that these properties should contain > values as listed in the examples below per each CMU. > This also applies to you following series of 9 patches. OK, I'll add more following information: I'll send only patch1 with following information. + - clocks: list of clock identifiers which are fed as the input to + the given clock controller. Please refer the next section to + find the input clocks for a given controller. + +- clock-names: list of names of clocks which are fed as the input + to the given clock controller. + + Input clocks for top clock controller: + - oscclk + - sclk_mphy_pll + - sclk_mfc_pll + - sclk_bus_pll + + Input clocks for cpif clock controller: + - oscclk + + Input clocks for mif clock controller: + - oscclk + - sclk_mphy_pll + + Input clocks for fsys clock controller: + - oscclk + - sclk_ufs_mphy + - div_aclk_fsys_200 + - sclk_pcie_100_fsys + - sclk_ufsunipro_fsys + - sclk_mmc2_fsys + - sclk_mmc1_fsys + - sclk_mmc0_fsys + - sclk_usbhost30_fsys + - sclk_usbdrd30_fsys + + Input clocks for g2d clock controller: + - oscclk + - aclk_g2d_266 + - aclk_g2d_400 + + Input clocks for disp clock controller: + - oscclk + - sclk_dsim1_disp + - sclk_dsim0_disp + - sclk_dsd_disp + - sclk_decon_tv_eclk_disp + - sclk_decon_vclk_disp + - sclk_decon_eclk_disp + - sclk_decon_tv_vclk_disp + - aclk_disp_333 + + Input clocks for bus0 clock controller: + - aclk_bus0_400 + + Input clocks for bus1 clock controller: + - aclk_bus1_400 + + Input clocks for bus2 clock controller: + - oscclk + - aclk_bus2_400 + + Input clocks for g3d clock controller: + - oscclk + - aclk_g3d_400 + + Input clocks for gscl clock controller: + - oscclk + - aclk_gscl_111 + - aclk_gscl_333 > >> + >> +Each clock is assigned an identifier and client nodes can use this identifier >> +to specify the clock which they consume. >> + >> +All available clocks are defined as preprocessor macros in >> +dt-bindings/clock/exynos5433.h header and can be used in device >> +tree sources. >> + >> +Example 1: Examples of 'oscclk' source clock node are listed below. >> + >> + xxti: xxti { >> + compatible = "fixed-clock"; >> + clock-output-names = "oscclk"; >> + #clock-cells = <0>; >> + }; >> + >> +Example 2: Examples of clock controller nodes are listed below. >> + >> + cmu_top: clock-controller@0x10030000 { >> + compatible = "samsung,exynos5433-cmu-top"; >> + reg = <0x10030000 0x0c04>; >> + #clock-cells = <1>; >> + >> + clock-names = "oscclk", >> + "sclk_mphy_pll", >> + "sclk_mfc_pll", >> + "sclk_bus_pll"; >> + clocks = <&xxti>, >> + <&cmu_cpif CLK_SCLK_MPHY_PLL>, >> + <&cmu_mif CLK_SCLK_MFC_PLL>, >> + <&cmu_mif CLK_SCLK_BUS_PLL>; >> + }; > >> + cmu_gscl: clock-controller@0x13cf0000 { >> + compatible = "samsung,exynos5433-cmu-gscl"; >> + reg = <0x13cf0000 0x0b10>; >> + #clock-cells = <1>; >> + >> + clock-names = "oscclk", >> + "aclk_gscl_111", >> + "aclk_gscl_333"; >> + clocks = <&xxti>, >> + <&cmu_top CLK_ACLK_GSCL_111>, >> + <&cmu_top CLK_ACLK_GSCL_333>; >> + }; >> + >> +Example 3: UART controller node that consumes the clock generated by the clock >> + controller. >> + >> + serial_0: serial@14C10000 { >> + compatible = "samsung,exynos5433-uart"; >> + reg = <0x14C10000 0x100>; >> + interrupts = <0 421 0>; >> + clocks = <&cmu_peric CLK_PCLK_UART0>, >> + <&cmu_peric CLK_SCLK_UART0>; >> + clock-names = "uart", "clk_uart_baud0"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart0_bus>; >> + status = "disabled"; >> + }; >> + >> +Example 4: SPI controller node that consumes the clock generated by the clock >> + controller. > > This fourth example doesn't look like it adds significant value, I'd say it > can be removed. OK, I'll merge it. > >> + spi_0: spi@14d20000 { >> + compatible = "samsung,exynos7-spi"; >> + reg = <0x14d20000 0x100>; >> + interrupts = <0 432 0>; >> + dmas = <&pdma0 9>, <&pdma0 8>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&cmu_peric CLK_PCLK_SPI0>, >> + <&cmu_top CLK_SCLK_SPI0_PERIC>; >> + clock-names = "spi", "spi_busclk0"; >> + samsung,spi-src-clk = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&spi0_bus>; >> + status = "disabled"; >> + }; >> > > Also please don't forget to Cc devicetree@vger.kernel.org next time. OK. Thanks, Chanwoo Choi