From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752339AbbBXCjG (ORCPT ); Mon, 23 Feb 2015 21:39:06 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:38212 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751837AbbBXCjB (ORCPT ); Mon, 23 Feb 2015 21:39:01 -0500 X-AuditID: cbfee690-f79ab6d0000046f7-2f-54ebe43c9057 Message-id: <54EBE43C.1020901@samsung.com> Date: Tue, 24 Feb 2015 11:38:52 +0900 From: Chanwoo Choi User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-version: 1.0 To: Krzysztof Kozlowski Cc: Kukjin Kim , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Kyungmin Park , Marek Szyprowski , stable@vger.kernel.org Subject: Re: [RESEND PATCH] ARM: EXYNOS: Fix failed second suspend on Exynos4 References: <1424256325-16659-1-git-send-email-k.kozlowski@samsung.com> In-reply-to: <1424256325-16659-1-git-send-email-k.kozlowski@samsung.com> Content-type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIIsWRmVeSWpSXmKPExsWyRsSkRNfmyesQg0/NWhavXxha9D9+zWxx tukNu8Wmx9dYLS7vmsNmMeP8PiaLtUfuslss2PiI0YHDY9OqTjaPzUvqPfq2rGL0+LxJLoAl issmJTUnsyy1SN8ugSvjVN8uloLJ5hVNV/vZGhgv6XQxcnJICJhI7D96gRnCFpO4cG89Wxcj F4eQwFJGifmPHjDCFLX1PmUFsYUEpjNKNPdUQhS9ZpR48Hw3WIJXQEti9+1eMJtFQFViW/8b NhCbDSi+/8UNMFtUIExi5fQrLBD1ghI/Jt8Ds0UEDCUO7t7OBDKUWeAfo8SXufvANgsL+Eo8 udUMVMQBtM1d4t2dNJAwp4CHxKp/p8FmMgvoSOxvnQZly0tsXvOWGWSOhMAxdok5Lx+wQxwk IPFt8iGwORICshKbDkB9LClxcMUNlgmMYrOQnDQLydhZSMYuYGRexSiaWpBcUJyUXmSiV5yY W1yal66XnJ+7iREYc6f/PZuwg/HeAetDjAIcjEo8vA25r0KEWBPLiitzDzGaAl0xkVlKNDkf GNl5JfGGxmZGFqYmpsZG5pZmSuK8r6V+BgsJpCeWpGanphakFsUXleakFh9iZOLglGpgXCwR x2/6/9efuwH5hxnsX8xYYtlaOF/nBcf5zuvfzINnvm2rcc37Uf0vxbznWJz+xOPzxT5zHs0J 5KtmfN+2Z3dnhb7OJo6bOXv4d0UlPd1xd+qNsmXdT3l5WFoOcvSe2rrS/EXmmle1mtEi6cUS Sq4bDKaWLTQocttbcDTWxnZV5tJnrKL2SizFGYmGWsxFxYkAsX/a4LQCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsVy+t9jQV2bJ69DDPZfV7B4/cLQov/xa2aL s01v2C02Pb7GanF51xw2ixnn9zFZrD1yl91iwcZHjA4cHptWdbJ5bF5S79G3ZRWjx+dNcgEs UQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAVygp lCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCWsYM0717WIpmGxe0XS1n62B8ZJO FyMnh4SAiURb71NWCFtM4sK99WwgtpDAdEaJ5p7KLkYuIPs1o8SD57vBingFtCR23+4Fs1kE VCW29b8Ba2ADiu9/cQPMFhUIk1g5/QoLRL2gxI/J98BsEQFDiYO7tzOBDGUW+Mco8WXuPkaQ hLCAr8STW81ARRxA29wl3t1JAwlzCnhIrPp3Gmwms4COxP7WaVC2vMTmNW+ZJzAKzEKyYhaS sllIyhYwMq9iFE0tSC4oTkrPNdQrTswtLs1L10vOz93ECI7oZ1I7GFc2WBxiFOBgVOLhbch9 FSLEmlhWXJl7iFGCg1lJhHf2wdchQrwpiZVVqUX58UWlOanFhxhNgSEwkVlKNDkfmGzySuIN jU3MjCyNzA0tjIzNlcR5lezbQoQE0hNLUrNTUwtSi2D6mDg4pRoY584PW7vN5taqVPV/r6cc jdZ09cjK4y553XrDTI/FdfK/5vdSjxZHVmc+ZVmvwbJvX5dK59Ok3xp8OceF/7zqmDBNrOal wep3RoFH2iWYJvP7JTz8cMY1mdmmQ7hoedzfk8vWPm6Z6/CLd1bLxVOlPmekcqUkLuf8WDap 82QG08OtwYGXmXbdV2Ipzkg01GIuKk4EABHVjhD+AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Krzysztof, I tested this patch for suspend-to-ram on Exynos4412-based trats2 board. When I tested suspend-to-ram repetitively, I faced on hang issue of suspend-to-ram for Exynos4 as before. Could you send .config file for test? Thanks, Chanwoo Choi On 02/18/2015 07:45 PM, Krzysztof Kozlowski wrote: > On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in > 56b60b8bce4a ("ARM: 8265/1: dts: exynos4: Add nodes for L2 cache > controller") the second suspend to RAM failed. First suspend worked fine > but the next one hang just after powering down of secondary CPUs (system > consumed energy as it would be running but was not responsive). > > The issue was caused by enabling delayed reset assertion for CPU0 just > after issuing power down of cores. This was introduced for Exynos4 in > 13cfa6c4f7fa ("ARM: EXYNOS: Fix CPU idle clock down after CPU off"). > > The whole behavior is not well documented but after checking with vendor > code this should be done like this (on Exynos4): > 1. Enable delayed reset assertion when system is running (for all CPUs). > 2. Disable delayed reset assertion before suspending the system. > This can be done after powering off secondary CPUs. > 3. Re-enable the delayed reset assertion when system is resumed. > > Signed-off-by: Krzysztof Kozlowski > Fixes: 13cfa6c4f7fa ("ARM: EXYNOS: Fix CPU idle clock down after CPU off") > Cc: > --- > arch/arm/mach-exynos/common.h | 2 ++ > arch/arm/mach-exynos/exynos.c | 27 +++++++++++++++++++++++++++ > arch/arm/mach-exynos/platsmp.c | 39 ++------------------------------------- > arch/arm/mach-exynos/suspend.c | 3 +++ > 4 files changed, 34 insertions(+), 37 deletions(-) > > diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h > index f70eca7ee705..0ef8d4b47102 100644 > --- a/arch/arm/mach-exynos/common.h > +++ b/arch/arm/mach-exynos/common.h > @@ -153,6 +153,8 @@ extern void exynos_enter_aftr(void); > > extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data; > > +extern void exynos_set_delayed_reset_assertion(bool enable); > + > extern void s5p_init_cpu(void __iomem *cpuid_addr); > extern unsigned int samsung_rev(void); > extern void __iomem *cpu_boot_reg_base(void); > diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c > index 2013f73797ed..e2f46295eed7 100644 > --- a/arch/arm/mach-exynos/exynos.c > +++ b/arch/arm/mach-exynos/exynos.c > @@ -166,6 +166,33 @@ static void __init exynos_init_io(void) > exynos_map_io(); > } > > +/* > + * Set or clear the USE_DELAYED_RESET_ASSERTION option. Used by smp code > + * and suspend. > + * > + * This is necessary only on Exynos4 SoCs. When system is running > + * USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down > + * feature could properly detect global idle state when secondary CPU is > + * powered down. > + * > + * However this should not be set when such system is going into suspend. > + */ > +void exynos_set_delayed_reset_assertion(bool enable) > +{ > + if (soc_is_exynos4()) { > + unsigned int tmp, core_id; > + > + for (core_id = 0; core_id < num_possible_cpus(); core_id++) { > + tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id)); > + if (enable) > + tmp |= S5P_USE_DELAYED_RESET_ASSERTION; > + else > + tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION); > + pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id)); > + } > + } > +} > + > static const struct of_device_id exynos_dt_pmu_match[] = { > { .compatible = "samsung,exynos3250-pmu" }, > { .compatible = "samsung,exynos4210-pmu" }, > diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c > index 3f32c47a6d74..19d5c87c842c 100644 > --- a/arch/arm/mach-exynos/platsmp.c > +++ b/arch/arm/mach-exynos/platsmp.c > @@ -34,30 +34,6 @@ > > extern void exynos4_secondary_startup(void); > > -/* > - * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs > - * during hot-(un)plugging CPUx. > - * > - * The feature can be cleared safely during first boot of secondary CPU. > - * > - * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering > - * down a CPU so the CPU idle clock down feature could properly detect global > - * idle state when CPUx is off. > - */ > -static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable) > -{ > - if (soc_is_exynos4()) { > - unsigned int tmp; > - > - tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id)); > - if (enable) > - tmp |= S5P_USE_DELAYED_RESET_ASSERTION; > - else > - tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION); > - pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id)); > - } > -} > - > #ifdef CONFIG_HOTPLUG_CPU > static inline void cpu_leave_lowpower(u32 core_id) > { > @@ -73,8 +49,6 @@ static inline void cpu_leave_lowpower(u32 core_id) > : "=&r" (v) > : "Ir" (CR_C), "Ir" (0x40) > : "cc"); > - > - exynos_set_delayed_reset_assertion(core_id, false); > } > > static inline void platform_do_lowpower(unsigned int cpu, int *spurious) > @@ -87,14 +61,6 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) > /* Turn the CPU off on next WFI instruction. */ > exynos_cpu_power_down(core_id); > > - /* > - * Exynos4 SoCs require setting > - * USE_DELAYED_RESET_ASSERTION so the CPU idle > - * clock down feature could properly detect > - * global idle state when CPUx is off. > - */ > - exynos_set_delayed_reset_assertion(core_id, true); > - > wfi(); > > if (pen_release == core_id) { > @@ -355,9 +321,6 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) > udelay(10); > } > > - /* No harm if this is called during first boot of secondary CPU */ > - exynos_set_delayed_reset_assertion(core_id, false); > - > /* > * now the secondary core is starting up let it run its > * calibrations, then wait for it to finish > @@ -404,6 +367,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) > > exynos_sysram_init(); > > + exynos_set_delayed_reset_assertion(true); > + > if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) > scu_enable(scu_base_addr()); > > diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c > index 666ec3e5b03f..d4da035cc88a 100644 > --- a/arch/arm/mach-exynos/suspend.c > +++ b/arch/arm/mach-exynos/suspend.c > @@ -235,6 +235,8 @@ static void exynos_pm_enter_sleep_mode(void) > > static void exynos_pm_prepare(void) > { > + exynos_set_delayed_reset_assertion(false); > + > /* Set wake-up mask registers */ > exynos_pm_set_wakeup_mask(); > > @@ -383,6 +385,7 @@ early_wakeup: > > /* Clear SLEEP mode set in INFORM1 */ > pmu_raw_writel(0x0, S5P_INFORM1); > + exynos_set_delayed_reset_assertion(true); > } > > static void exynos3250_pm_resume(void) >