From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752842AbbCCF5r (ORCPT ); Tue, 3 Mar 2015 00:57:47 -0500 Received: from regular1.263xmail.com ([211.150.99.138]:52748 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752684AbbCCF5q (ORCPT ); Tue, 3 Mar 2015 00:57:46 -0500 X-Greylist: delayed 728 seconds by postgrey-1.27 at vger.kernel.org; Tue, 03 Mar 2015 00:57:46 EST X-263anti-spam: KSV:0;BIG:0;ABS:1;DNS:0;ATT:0;SPF:S; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ADDR-CHECKED: 0 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 103.29.143.42 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <54F54D55.8040200@rock-chips.com> Date: Tue, 03 Mar 2015 13:57:41 +0800 From: Chris Zhong User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: Heiko Stuebner CC: dianders@chromium.org, djkurtz@chromium.org, sonnyrao@chromium.org, linux-rockchip@lists.infradead.org, Daniel Kurtz , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] ARM: rockchip: disable watchdog during suspend References: <1423487543-10593-1-git-send-email-zyw@rock-chips.com> <1423487543-10593-2-git-send-email-zyw@rock-chips.com> <19262192.YHbflRWDXo@phil> In-Reply-To: <19262192.YHbflRWDXo@phil> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/03/2015 04:50 AM, Heiko Stuebner wrote: > Hi Chris, > > Am Montag, 9. Februar 2015, 21:12:23 schrieb Chris Zhong: >> The watchdog clock should be disable in dw_wdt_suspend, but we set a >> dummy clock to watchdog for rk3288. So the watchdog will continue to >> work during suspend. And we switch the system clock to 32khz from 24Mhz, >> during suspend, so the watchdog timer over count will increase to >> 755 times, about 12.5 hours, the original value is 60 seconds. So >> watchdog will reset the system over a night, but voltage are all >> incorrect, then it hang on reset. >> >> Signed-off-by: Chris Zhong >> Signed-off-by: Daniel Kurtz > The SGRF is not writeable in all bootmodes (I've talked with Doug about this > to verify I remembered this correctly), so handling the sgrf gate for the > watchdog is not safe for all possible boards. > > Why not simply turn off the watchdog in the driver during suspend? I think SGRF is writeable, since we would set this RK3288_SGRF_SOC_CON0 register when suspend. and this SGRF_PCLK_WDT_GATE is one bit of RK3288_SGRF_SOC_CON0. I tried to set wdt_en(WDT_CR[bit 0]) to 0 in watchdog driver, but that would cause system reboot. > > Heiko > >> --- >> >> arch/arm/mach-rockchip/pm.c | 11 ++++++++--- >> arch/arm/mach-rockchip/pm.h | 2 ++ >> 2 files changed, 10 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c >> index a3ab397..b07d886 100644 >> --- a/arch/arm/mach-rockchip/pm.c >> +++ b/arch/arm/mach-rockchip/pm.c >> @@ -75,9 +75,13 @@ static void rk3288_slp_mode_set(int level) >> regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, >> &rk3288_pmu_pwr_mode_con); >> >> - /* set bit 8 so that system will resume to FAST_BOOT_ADDR */ >> + /* >> + * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR >> + * PCLK_WDT_GATE - disable WDT during suspend. >> + */ >> regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, >> - SGRF_FAST_BOOT_EN | SGRF_FAST_BOOT_EN_WRITE); >> + SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN >> + | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE); >> >> /* booting address of resuming system is from this register value */ >> regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, >> @@ -122,7 +126,8 @@ static void rk3288_slp_mode_set_resume(void) >> rk3288_pmu_pwr_mode_con); >> >> regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, >> - rk3288_sgrf_soc_con0 | SGRF_FAST_BOOT_EN_WRITE); >> + rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE >> + | SGRF_FAST_BOOT_EN_WRITE); >> } >> >> static int rockchip_lpmode_enter(unsigned long arg) >> diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h >> index 96beaa0..d463978 100644 >> --- a/arch/arm/mach-rockchip/pm.h >> +++ b/arch/arm/mach-rockchip/pm.h >> @@ -44,6 +44,8 @@ void __init rockchip_suspend_init(void); >> >> #define RK3288_SGRF_SOC_CON0 (0x0000) >> #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) >> +#define SGRF_PCLK_WDT_GATE BIT(6) >> +#define SGRF_PCLK_WDT_GATE_WRITE BIT(22) >> #define SGRF_FAST_BOOT_EN BIT(8) >> #define SGRF_FAST_BOOT_EN_WRITE BIT(24) > > >