From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757482AbbCCSld (ORCPT ); Tue, 3 Mar 2015 13:41:33 -0500 Received: from eusmtp01.atmel.com ([212.144.249.243]:46119 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756643AbbCCSlb (ORCPT ); Tue, 3 Mar 2015 13:41:31 -0500 Message-ID: <54F6005D.6000308@atmel.com> Date: Tue, 3 Mar 2015 19:41:33 +0100 From: Nicolas Ferre Organization: atmel User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: Wenyou Yang CC: , , , , , Subject: Re: [PATCH 1/3] pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts References: <1423115977-5852-1-git-send-email-wenyou.yang@atmel.com> <1423116037-5921-1-git-send-email-wenyou.yang@atmel.com> In-Reply-To: <1423116037-5921-1-git-send-email-wenyou.yang@atmel.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.161.30.18] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 05/02/2015 07:00, Wenyou Yang a écrit : > From: Sylvain Rochet > > Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if > something went wrong instead of continuing in unknown condition. There > is not much we can do if a PLL lock never ends, we are running in SRAM > and we will not be able to connect back the sdram or ddram in order to > be able to fire up a message or just panic. > > As a bonus, not decounting the timeout register in slow clock mode > reduce cumulated suspend time and resume time from ~17ms to ~15ms. > > Signed-off-by: Sylvain Rochet > Acked-by: Wenyou.Yang Acked-by: Nicolas Ferre and stacked in at91-4.0-fixes. thanks! > --- > arch/arm/mach-at91/pm_slowclock.S | 33 ++++----------------------------- > 1 file changed, 4 insertions(+), 29 deletions(-) > > diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S > index 2001877..79dfdbe 100644 > --- a/arch/arm/mach-at91/pm_slowclock.S > +++ b/arch/arm/mach-at91/pm_slowclock.S > @@ -34,11 +34,6 @@ > */ > #undef SLOWDOWN_MASTER_CLOCK > > -#define MCKRDY_TIMEOUT 1000 > -#define MOSCRDY_TIMEOUT 1000 > -#define PLLALOCK_TIMEOUT 1000 > -#define PLLBLOCK_TIMEOUT 1000 > - > pmc .req r0 > sdramc .req r1 > ramc1 .req r2 > @@ -50,56 +45,36 @@ tmp2 .req r5 > * Wait until master clock is ready (after switching master clock source) > */ > .macro wait_mckrdy > - mov tmp2, #MCKRDY_TIMEOUT > -1: sub tmp2, tmp2, #1 > - cmp tmp2, #0 > - beq 2f > - ldr tmp1, [pmc, #AT91_PMC_SR] > +1: ldr tmp1, [pmc, #AT91_PMC_SR] > tst tmp1, #AT91_PMC_MCKRDY > beq 1b > -2: > .endm > > /* > * Wait until master oscillator has stabilized. > */ > .macro wait_moscrdy > - mov tmp2, #MOSCRDY_TIMEOUT > -1: sub tmp2, tmp2, #1 > - cmp tmp2, #0 > - beq 2f > - ldr tmp1, [pmc, #AT91_PMC_SR] > +1: ldr tmp1, [pmc, #AT91_PMC_SR] > tst tmp1, #AT91_PMC_MOSCS > beq 1b > -2: > .endm > > /* > * Wait until PLLA has locked. > */ > .macro wait_pllalock > - mov tmp2, #PLLALOCK_TIMEOUT > -1: sub tmp2, tmp2, #1 > - cmp tmp2, #0 > - beq 2f > - ldr tmp1, [pmc, #AT91_PMC_SR] > +1: ldr tmp1, [pmc, #AT91_PMC_SR] > tst tmp1, #AT91_PMC_LOCKA > beq 1b > -2: > .endm > > /* > * Wait until PLLB has locked. > */ > .macro wait_pllblock > - mov tmp2, #PLLBLOCK_TIMEOUT > -1: sub tmp2, tmp2, #1 > - cmp tmp2, #0 > - beq 2f > - ldr tmp1, [pmc, #AT91_PMC_SR] > +1: ldr tmp1, [pmc, #AT91_PMC_SR] > tst tmp1, #AT91_PMC_LOCKB > beq 1b > -2: > .endm > > .text > -- Nicolas Ferre