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Date: Tue, 03 Mar 2015 15:24:30 -0800
From: David Daney <ddaney.cavm@gmail.com>
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To: Ben Hutchings <ben@decadent.org.uk>
CC: linux-kernel@vger.kernel.org, stable@vger.kernel.org,
        akpm@linux-foundation.org, linux-mips@linux-mips.org,
        Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>,
        David Daney <david.daney@cavium.com>,
        Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH 3.2 12/24] MIPS: Fix C0_Pagegrain[IEC] support.
References: <lsq.1425420688.25339415@decadent.org.uk>
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On 03/03/2015 02:11 PM, Ben Hutchings wrote:
> 3.2.68-rc1 review patch.  If anyone has any objections, please let me know.
>

I object!

Because ...

> ------------------
>
> From: David Daney <david.daney@cavium.com>
>
> commit 9ead8632bbf454cfc709b6205dc9cd8582fb0d64 upstream.
>
> The following commits:
>
>    5890f70f15c52d (MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions)
>    6575b1d4173eae (MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions)
>
> break the kernel for *all* existing MIPS CPUs that implement the
> CP0_PageGrain[IEC] bit.  They cause the TLB exception handlers to be
> generated without the legacy execute-inhibit handling, but never set
> the CP0_PageGrain[IEC] bit to activate the use of dedicated exception
> vectors for execute-inhibit exceptions.  The result is that upon
> detection of an execute-inhibit violation, we loop forever in the TLB
> exception handlers instead of sending SIGSEGV to the task.
>
> If we are generating TLB exception handlers expecting separate
> vectors, we must also enable the CP0_PageGrain[IEC] feature.
>
> The bug was introduced in kernel version 3.17.

... I don't think the patch should be applied to versions prior to 3.17

David Daney

>
> Signed-off-by: David Daney <david.daney@cavium.com>
> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Cc: linux-mips@linux-mips.org
> Patchwork: http://patchwork.linux-mips.org/patch/8880/
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
> Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
> ---
>   arch/mips/mm/tlb-r4k.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> --- a/arch/mips/mm/tlb-r4k.c
> +++ b/arch/mips/mm/tlb-r4k.c
> @@ -447,6 +447,8 @@ void __cpuinit tlb_init(void)
>   #ifdef CONFIG_64BIT
>   		pg |= PG_ELPA;
>   #endif
> +		if (cpu_has_rixiex)
> +			pg |= PG_IEC;
>   		write_c0_pagegrain(pg);
>   	}
>
>
>
>
>