From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932399AbbCIP4m (ORCPT ); Mon, 9 Mar 2015 11:56:42 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:35353 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753867AbbCIP4i (ORCPT ); Mon, 9 Mar 2015 11:56:38 -0400 Message-ID: <54FDC2A8.2010301@pengutronix.de> Date: Mon, 09 Mar 2015 16:56:24 +0100 From: Marc Kleine-Budde User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:34.0) Gecko/20100101 Icedove/34.0 MIME-Version: 1.0 To: =?UTF-8?Q?S=c3=b6ren_Brinkmann?= , Michal Simek CC: Jean Delvare , linux-kernel@vger.kernel.org, monstr@monstr.eu, Wolfgang Grandegger , linux-can@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH] net: can: Enable xilinx driver for all ARCHs References: <4096fa4ceae72817d8e64d9a1da738038a5c864a.1425890926.git.michal.simek@xilinx.com> <54FD5EE1.6050402@pengutronix.de> <54FD641C.7090607@pengutronix.de> <54FD6E42.6070206@pengutronix.de> <1425909239.23920.60.camel@chaos.site> <54FDA662.8020801@pengutronix.de> In-Reply-To: Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="q3jhJwn44h2amAQONvpGN1C1EnFjTAdDB" X-SA-Exim-Connect-IP: 2001:6f8:1178:4:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: mkl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --q3jhJwn44h2amAQONvpGN1C1EnFjTAdDB Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On 03/09/2015 04:51 PM, S=C3=B6ren Brinkmann wrote: >>> Sounds reasonable. Michael, make it so. >> >> I have sent v2 which add arm64 to Kconfig and I am keeping just depend= ency on >> ARCH_ZYNQ not all ARM platforms. >=20 > You could (and some people do that with some devices) use these devices= > from x86(_64) if you plug your FPGA/Zynq platform into a PCIe slot > (FWIW, this should work for any platform that supports PCIe). I think w= e > just had somebody sending patches to enable the Zynq UART, IIRC, for x8= 6. Nice :) The "depends on" can easily be changed with once there's PCIe glue code for the driver. Marc --=20 Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions | Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de | --q3jhJwn44h2amAQONvpGN1C1EnFjTAdDB Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCgAGBQJU/cKuAAoJECte4hHFiupUFGcQAILvkTRI6pdrZYq/ea/cE8N4 gLyTqXxTKR+5Lx3WClV54X9YW509LxWc6b+V9Sw6xL/QvbG2kvJKBnfGLvsLSThl wPMyB3YfYll1VNEy5YKAhZijHqBrPUQ0xTGG7MGdt2euXubdrKt3VMEB4PW8wXxo Ypt1+5NJDhhF8uO9yzYA3KeWUhmd4bnH6x8w/4HIvnPYjsM/TmmD5PGjdYxlO2Hv XvWvCIlz6fnU6U9YtjcEpAeradIVTNwE1sxSGg7lFxO6B5ofT2KbtpRlRT5poJkb zz8qdcES2Dn/e5TMwxYE5LjPTthc8Jx1EbqeJdr3KZcV+BNGZk7mE4O3NaZNACu3 aKMwN6PoIllZDVhedtwyXY69ZcYi31CW6bSrEn+eSxWhK9mQBWwg3vRC5Q73waWN HBh0BrQI+kAgaH+kU1I73hhtHoUiP080gl2BqSaywv9Wh34p85AcpVCy85ocomCI PinCN0rRfDG9naQMihHK04AlOP8LG4Ypk0mVzdaKThRS2GkWNudhaRGBYqWvXUML JWCtD1igMYp1n40xcg6aEuz6MkM8AOpxYkJge31mNP4v2lK4ulOYW+3i7sUPmP7P MeBsMvr7k7nJGHT4luatk8M+K5j5eD1oT1RhWwb4Xyf8UzHohBgKeaV1fqaV/SGV G3lQVYw8kk1VJOm8hACr =JftJ -----END PGP SIGNATURE----- --q3jhJwn44h2amAQONvpGN1C1EnFjTAdDB--